2 * (C) Copyright 2001-2003
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * Modified during 2001 by
6 * Advanced Communications Technologies (Australia) Pty. Ltd.
7 * Howard Walker, Tuong Vu-Dinh
9 * (C) Copyright 2001, Stuart Hughes, Lineo Inc, stuarth@lineo.com
10 * Added support for the 16M dram simm on the 8260ads boards
12 * (C) Copyright 2003-2004 Arabella Software Ltd.
13 * Yuli Barcohen <yuli@arabellasw.com>
14 * Added support for SDRAM DIMMs SPD EEPROM, MII, Ethernet PHY init.
16 * Copyright (c) 2005 MontaVista Software, Inc.
17 * Vitaly Bordug <vbordug@ru.mvista.com>
18 * Added support for PCI.
20 * See file CREDITS for list of people who contributed to this
23 * This program is free software; you can redistribute it and/or
24 * modify it under the terms of the GNU General Public License as
25 * published by the Free Software Foundation; either version 2 of
26 * the License, or (at your option) any later version.
28 * This program is distributed in the hope that it will be useful,
29 * but WITHOUT ANY WARRANTY; without even the implied warranty of
30 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
31 * GNU General Public License for more details.
33 * You should have received a copy of the GNU General Public License
34 * along with this program; if not, write to the Free Software
35 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
42 #include <asm/m8260_pci.h>
49 #ifdef CONFIG_OF_LIBFDT
51 #include <fdt_support.h>
55 * I/O Port configuration table
57 * if conf is 1, then that port pin will be configured at boot time
58 * according to the five values podr/pdir/ppar/psor/pdat for that entry
61 #define CONFIG_SYS_FCC1 (CONFIG_ETHER_INDEX == 1)
62 #define CONFIG_SYS_FCC2 (CONFIG_ETHER_INDEX == 2)
63 #define CONFIG_SYS_FCC3 (CONFIG_ETHER_INDEX == 3)
65 const iop_conf_t iop_conf_tab[4][32] = {
67 /* Port A configuration */
68 { /* conf ppar psor pdir podr pdat */
69 /* PA31 */ { CONFIG_SYS_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII COL */
70 /* PA30 */ { CONFIG_SYS_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII CRS */
71 /* PA29 */ { CONFIG_SYS_FCC1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_ER */
72 /* PA28 */ { CONFIG_SYS_FCC1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_EN */
73 /* PA27 */ { CONFIG_SYS_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_DV */
74 /* PA26 */ { CONFIG_SYS_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_ER */
75 /* PA25 */ { 0, 0, 0, 0, 0, 0 }, /* PA25 */
76 /* PA24 */ { 0, 0, 0, 0, 0, 0 }, /* PA24 */
77 /* PA23 */ { 0, 0, 0, 0, 0, 0 }, /* PA23 */
78 /* PA22 */ { 0, 0, 0, 0, 0, 0 }, /* PA22 */
79 /* PA21 */ { CONFIG_SYS_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[3] */
80 /* PA20 */ { CONFIG_SYS_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[2] */
81 /* PA19 */ { CONFIG_SYS_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[1] */
82 /* PA18 */ { CONFIG_SYS_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[0] */
83 /* PA17 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[0] */
84 /* PA16 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[1] */
85 /* PA15 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[2] */
86 /* PA14 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[3] */
87 /* PA13 */ { 0, 0, 0, 0, 0, 0 }, /* PA13 */
88 /* PA12 */ { 0, 0, 0, 0, 0, 0 }, /* PA12 */
89 /* PA11 */ { 0, 0, 0, 0, 0, 0 }, /* PA11 */
90 /* PA10 */ { 0, 0, 0, 0, 0, 0 }, /* PA10 */
91 /* PA9 */ { 0, 0, 0, 0, 0, 0 }, /* PA9 */
92 /* PA8 */ { 0, 0, 0, 0, 0, 0 }, /* PA8 */
93 /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
94 /* PA6 */ { 0, 0, 0, 0, 0, 0 }, /* PA6 */
95 /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
96 /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
97 /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
98 /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
99 /* PA1 */ { 0, 0, 0, 0, 0, 0 }, /* PA1 */
100 /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
103 /* Port B configuration */
104 { /* conf ppar psor pdir podr pdat */
105 /* PB31 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
106 /* PB30 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
107 /* PB29 */ { CONFIG_SYS_FCC2, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
108 /* PB28 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
109 /* PB27 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
110 /* PB26 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
111 /* PB25 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
112 /* PB24 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
113 /* PB23 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
114 /* PB22 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
115 /* PB21 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
116 /* PB20 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
117 /* PB19 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
118 /* PB18 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
119 /* PB17 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */
120 /* PB16 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */
121 /* PB15 */ { CONFIG_SYS_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */
122 /* PB14 */ { CONFIG_SYS_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */
123 /* PB13 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:COL */
124 /* PB12 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:CRS */
125 /* PB11 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
126 /* PB10 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
127 /* PB9 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
128 /* PB8 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
129 /* PB7 */ { CONFIG_SYS_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
130 /* PB6 */ { CONFIG_SYS_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
131 /* PB5 */ { CONFIG_SYS_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
132 /* PB4 */ { CONFIG_SYS_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
133 /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
134 /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
135 /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
136 /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
140 { /* conf ppar psor pdir podr pdat */
141 /* PC31 */ { 0, 0, 0, 0, 0, 0 }, /* PC31 */
142 /* PC30 */ { 0, 0, 0, 0, 0, 0 }, /* PC30 */
143 /* PC29 */ { 0, 0, 0, 0, 0, 0 }, /* PC29 */
144 /* PC28 */ { 0, 0, 0, 0, 0, 0 }, /* PC28 */
145 /* PC27 */ { 0, 0, 0, 0, 0, 0 }, /* PC27 */
146 /* PC26 */ { 0, 0, 0, 0, 0, 0 }, /* PC26 */
147 /* PC25 */ { 0, 0, 0, 0, 0, 0 }, /* PC25 */
148 /* PC24 */ { 0, 0, 0, 0, 0, 0 }, /* PC24 */
149 /* PC23 */ { 0, 0, 0, 0, 0, 0 }, /* PC23 */
150 /* PC22 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII Tx Clock (CLK10) */
151 /* PC21 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII Rx Clock (CLK11) */
152 /* PC20 */ { 0, 0, 0, 0, 0, 0 }, /* PC20 */
153 #if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS
154 /* PC19 */ { 1, 0, 0, 1, 0, 0 }, /* FETHMDC */
155 /* PC18 */ { 1, 0, 0, 0, 0, 0 }, /* FETHMDIO */
156 /* PC17 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII Rx Clock (CLK15) */
157 /* PC16 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII Tx Clock (CLK16) */
159 /* PC19 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII Rx Clock (CLK13) */
160 /* PC18 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII Tx Clock (CLK14) */
161 /* PC17 */ { 0, 0, 0, 0, 0, 0 }, /* PC17 */
162 /* PC16 */ { 0, 0, 0, 0, 0, 0 }, /* PC16 */
163 #endif /* CONFIG_ADSTYPE == CONFIG_SYS_8272ADS */
164 /* PC15 */ { 0, 0, 0, 0, 0, 0 }, /* PC15 */
165 /* PC14 */ { 0, 0, 0, 0, 0, 0 }, /* PC14 */
166 /* PC13 */ { 0, 0, 0, 0, 0, 0 }, /* PC13 */
167 /* PC12 */ { 0, 0, 0, 0, 0, 0 }, /* PC12 */
168 /* PC11 */ { 0, 0, 0, 0, 0, 0 }, /* PC11 */
169 #if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS
170 /* PC10 */ { 0, 0, 0, 0, 0, 0 }, /* PC10 */
171 /* PC9 */ { 0, 0, 0, 0, 0, 0 }, /* PC9 */
173 /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* FETHMDC */
174 /* PC9 */ { 1, 0, 0, 0, 0, 0 }, /* FETHMDIO */
175 #endif /* CONFIG_ADSTYPE == CONFIG_SYS_8272ADS */
176 /* PC8 */ { 0, 0, 0, 0, 0, 0 }, /* PC8 */
177 /* PC7 */ { 0, 0, 0, 0, 0, 0 }, /* PC7 */
178 /* PC6 */ { 0, 0, 0, 0, 0, 0 }, /* PC6 */
179 /* PC5 */ { 0, 0, 0, 0, 0, 0 }, /* PC5 */
180 /* PC4 */ { 0, 0, 0, 0, 0, 0 }, /* PC4 */
181 /* PC3 */ { 0, 0, 0, 0, 0, 0 }, /* PC3 */
182 /* PC2 */ { 0, 0, 0, 0, 0, 0 }, /* PC2 */
183 /* PC1 */ { 0, 0, 0, 0, 0, 0 }, /* PC1 */
184 /* PC0 */ { 0, 0, 0, 0, 0, 0 }, /* PC0 */
188 { /* conf ppar psor pdir podr pdat */
189 /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 UART RxD */
190 /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 UART TxD */
191 /* PD29 */ { 0, 0, 0, 0, 0, 0 }, /* PD29 */
192 /* PD28 */ { 0, 1, 0, 0, 0, 0 }, /* PD28 */
193 /* PD27 */ { 0, 1, 1, 1, 0, 0 }, /* PD27 */
194 /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */
195 /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */
196 /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */
197 /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */
198 /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */
199 /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */
200 /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */
201 /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
202 /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */
203 /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */
204 /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */
205 /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */
206 /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */
207 /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
208 /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
209 /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
210 /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
211 /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
212 /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
213 /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */
214 /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
215 /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */
216 /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */
217 /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
218 /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
219 /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
220 /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
224 void reset_phy (void)
226 vu_long *bcsr = (vu_long *)CONFIG_SYS_BCSR;
229 #if CONFIG_SYS_PHY_ADDR == 0
230 bcsr[1] &= ~(FETHIEN1 | FETH1_RST);
232 bcsr[1] |= FETH1_RST;
234 bcsr[3] &= ~(FETHIEN2 | FETH2_RST);
236 bcsr[3] |= FETH2_RST;
237 #endif /* CONFIG_SYS_PHY_ADDR == 0 */
240 #if CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS
242 * Do not bypass Rx/Tx (de)scrambler (fix configuration error)
243 * Enable autonegotiation.
245 bb_miiphy_write(NULL, CONFIG_SYS_PHY_ADDR, 16, 0x610);
246 bb_miiphy_write(NULL, CONFIG_SYS_PHY_ADDR, PHY_BMCR,
247 PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
250 * Ethernet PHY is configured (by means of configuration pins)
251 * to work at 10Mb/s only. We reconfigure it using MII
252 * to advertise all capabilities, including 100Mb/s, and
253 * restart autonegotiation.
256 /* Advertise all capabilities */
257 bb_miiphy_write(NULL, CONFIG_SYS_PHY_ADDR, PHY_ANAR, 0x01E1);
259 /* Do not bypass Rx/Tx (de)scrambler */
260 bb_miiphy_write(NULL, CONFIG_SYS_PHY_ADDR, PHY_DCR, 0x0000);
262 bb_miiphy_write(NULL, CONFIG_SYS_PHY_ADDR, PHY_BMCR,
263 PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
264 #endif /* CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS */
265 #endif /* CONFIG_MII */
269 typedef struct pci_ic_s {
270 unsigned long pci_int_stat;
271 unsigned long pci_int_mask;
275 int board_early_init_f (void)
277 vu_long *bcsr = (vu_long *)CONFIG_SYS_BCSR;
280 volatile pci_ic_t* pci_ic = (pci_ic_t *) CONFIG_SYS_PCI_INT;
282 /* mask alll the PCI interrupts */
283 pci_ic->pci_int_mask |= 0xfff00000;
285 #if (CONFIG_CONS_INDEX == 1) || (CONFIG_KGDB_INDEX == 1)
286 bcsr[1] &= ~RS232EN_1;
288 #if (CONFIG_CONS_INDEX > 1) || (CONFIG_KGDB_INDEX > 1)
289 bcsr[1] &= ~RS232EN_2;
292 #if CONFIG_ADSTYPE != CONFIG_SYS_8260ADS /* PCI mode can be selected */
293 #if CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS
294 if ((bcsr[3] & BCSR_PCI_MODE) == 0) /* PCI mode selected by JP9 */
295 #endif /* CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS */
297 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
299 immap->im_clkrst.car_sccr |= M826X_SCCR_PCI_MODE_EN;
300 immap->im_siu_conf.sc_siumcr =
301 (immap->im_siu_conf.sc_siumcr & ~SIUMCR_LBPC11)
304 #endif /* CONFIG_ADSTYPE != CONFIG_SYS_8260ADS */
309 #define ns2clk(ns) (ns / (1000000000 / CONFIG_8260_CLKIN) + 1)
311 phys_size_t initdram (int board_type)
313 #if CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS
315 #elif CONFIG_ADSTYPE == CONFIG_SYS_8272ADS
321 #ifndef CONFIG_SYS_RAMBOOT
322 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
323 volatile memctl8260_t *memctl = &immap->im_memctl;
324 volatile uchar *ramaddr, c = 0xff;
331 immap->im_siu_conf.sc_ppc_acr = 0x00000002;
332 immap->im_siu_conf.sc_ppc_alrh = 0x01267893;
333 immap->im_siu_conf.sc_tescr1 = 0x00004000;
335 memctl->memc_mptpr = CONFIG_SYS_MPTPR;
336 #ifdef CONFIG_SYS_LSDRAM_BASE
338 Initialise local bus SDRAM only if the pins
339 are configured as local bus pins and not as PCI.
340 The configuration is determined by the HRCW.
342 if ((immap->im_siu_conf.sc_siumcr & SIUMCR_LBPC11) == SIUMCR_LBPC00) {
343 memctl->memc_lsrt = CONFIG_SYS_LSRT;
344 #if CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS /* CS3 */
345 memctl->memc_or3 = 0xFF803280;
346 memctl->memc_br3 = CONFIG_SYS_LSDRAM_BASE | 0x00001861;
348 memctl->memc_or4 = 0xFFC01480;
349 memctl->memc_br4 = CONFIG_SYS_LSDRAM_BASE | 0x00001861;
350 #endif /* CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS */
351 memctl->memc_lsdmr = CONFIG_SYS_LSDMR | 0x28000000;
352 ramaddr = (uchar *) CONFIG_SYS_LSDRAM_BASE;
354 memctl->memc_lsdmr = CONFIG_SYS_LSDMR | 0x08000000;
355 for (i = 0; i < 8; i++)
357 memctl->memc_lsdmr = CONFIG_SYS_LSDMR | 0x18000000;
359 memctl->memc_lsdmr = CONFIG_SYS_LSDMR | 0x40000000;
361 #endif /* CONFIG_SYS_LSDRAM_BASE */
363 /* Init 60x bus SDRAM */
364 #ifdef CONFIG_SPD_EEPROM
367 uint pbi, bsel, rowst, lsb, tmp;
369 i2c_read (CONFIG_SPD_ADDR, 0, 1, (uchar *) & spd, sizeof (spd));
371 /* Bank-based interleaving is not supported for physical bank
372 sizes greater than 128MB which is encoded as 0x20 in SPD
374 pbi = (spd.row_dens > 32) ? 1 : CONFIG_SDRAM_PBI;
375 msize = spd.nrows * (4 * spd.row_dens); /* Mixed size not supported */
376 or = ~(msize - 1) << 20; /* SDAM */
377 switch (spd.nbanks) { /* BPD */
390 lsb = 3; /* For 64-bit port, lsb is 3 bits */
392 if (pbi) { /* Bus partition depends on interleaving */
393 rowst = 32 - (spd.nrow_addr + spd.ncol_addr + bsel + lsb);
394 or |= (rowst << 9); /* ROWST */
396 rowst = 32 - (spd.nrow_addr + spd.ncol_addr + lsb);
397 or |= ((rowst * 2 - 12) << 9); /* ROWST */
399 or |= ((spd.nrow_addr - 9) << 6); /* NUMR */
401 psdmr = (pbi << 31); /* PBI */
402 /* Bus multiplexing parameters */
403 tmp = 32 - (lsb + spd.nrow_addr); /* Tables 10-19 and 10-20 */
404 psdmr |= ((tmp - (rowst - 5) - 13) << 24); /* SDAM */
405 psdmr |= ((tmp - 3 - 12) << 21); /* BSMA */
407 tmp = (31 - lsb - 10) - tmp;
408 /* Pin connected to SDA10 is (31 - lsb - 10).
409 rowst is multiplexed over (32 - (lsb + spd.nrow_addr)),
410 so (rowst + tmp) alternates with AP.
412 if (pbi) /* Table 10-7 */
413 psdmr |= ((10 - (rowst + tmp)) << 18); /* SDA10 */
415 psdmr |= ((12 - (rowst + tmp)) << 18); /* SDA10 */
417 /* SDRAM device-specific parameters */
418 tmp = ns2clk (70); /* Refresh recovery is not in SPD, so assume 70ns */
419 switch (tmp) { /* RFRC */
430 psdmr |= ((tmp - 2) << 15);
435 psdmr |= (ns2clk (spd.trp) % 8 << 12); /* PRETOACT */
436 psdmr |= (ns2clk (spd.trcd) % 8 << 9); /* ACTTORW */
437 /* BL=0 because for 64-bit SDRAM burst length must be 4 */
439 for (i = 0, tmp = spd.write_lat; (i < 4) && ((tmp & 1) == 0); i++)
441 switch (i) { /* WRC */
451 /* EAMUX=0 - no external address multiplexing */
452 /* BUFCMD=0 - no external buffers */
453 for (i = 1, tmp = spd.cas_lat; (i < 3) && ((tmp & 1) == 0); i++)
457 switch (spd.refresh & 0x7F) {
476 psrt = tmp / (1000000000 / CONFIG_8260_CLKIN *
477 ((memctl->memc_mptpr >> 8) + 1)) - 1;
479 printf ("\nDIMM type: %-18.18s\n", spd.mpart);
480 printf ("SPD size: %d\n", spd.info_size);
481 printf ("EEPROM size: %d\n", 1 << spd.chip_size);
482 printf ("Memory type: %d\n", spd.mem_type);
483 printf ("Row addr: %d\n", spd.nrow_addr);
484 printf ("Column addr: %d\n", spd.ncol_addr);
485 printf ("# of rows: %d\n", spd.nrows);
486 printf ("Row density: %d\n", spd.row_dens);
487 printf ("# of banks: %d\n", spd.nbanks);
488 printf ("Data width: %d\n",
489 256 * spd.dataw_msb + spd.dataw_lsb);
490 printf ("Chip width: %d\n", spd.primw);
491 printf ("Refresh rate: %02X\n", spd.refresh);
492 printf ("CAS latencies: %02X\n", spd.cas_lat);
493 printf ("Write latencies: %02X\n", spd.write_lat);
494 printf ("tRP: %d\n", spd.trp);
495 printf ("tRCD: %d\n", spd.trcd);
497 printf ("OR=%X, PSDMR=%08X, PSRT=%0X\n", or, psdmr, psrt);
498 #endif /* SPD_DEBUG */
500 #else /* !CONFIG_SPD_EEPROM */
502 psdmr = CONFIG_SYS_PSDMR;
503 psrt = CONFIG_SYS_PSRT;
504 #endif /* CONFIG_SPD_EEPROM */
505 memctl->memc_psrt = psrt;
506 memctl->memc_or2 = or;
507 memctl->memc_br2 = CONFIG_SYS_SDRAM_BASE | 0x00000041;
508 ramaddr = (uchar *) CONFIG_SYS_SDRAM_BASE;
509 memctl->memc_psdmr = psdmr | 0x28000000; /* Precharge all banks */
511 memctl->memc_psdmr = psdmr | 0x08000000; /* CBR refresh */
512 for (i = 0; i < 8; i++)
515 memctl->memc_psdmr = psdmr | 0x18000000; /* Mode Register write */
517 memctl->memc_psdmr = psdmr | 0x40000000; /* Refresh enable */
519 #endif /* CONFIG_SYS_RAMBOOT */
521 /* return total 60x bus SDRAM size */
522 return (msize * 1024 * 1024);
525 int checkboard (void)
527 #if CONFIG_ADSTYPE == CONFIG_SYS_8260ADS
528 puts ("Board: Motorola MPC8260ADS\n");
529 #elif CONFIG_ADSTYPE == CONFIG_SYS_8266ADS
530 puts ("Board: Motorola MPC8266ADS\n");
531 #elif CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS
532 puts ("Board: Motorola PQ2FADS-ZU\n");
533 #elif CONFIG_ADSTYPE == CONFIG_SYS_8272ADS
534 puts ("Board: Motorola MPC8272ADS\n");
536 puts ("Board: unknown\n");
542 struct pci_controller hose;
544 extern void pci_mpc8250_init(struct pci_controller *);
546 void pci_init_board(void)
548 pci_mpc8250_init(&hose);
552 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
553 void ft_board_setup(void *blob, bd_t *bd)
555 ft_cpu_setup(blob, bd);
557 ft_pci_setup(blob, bd);