2 * Copyright (C) 2010 Freescale Semiconductor, Inc.
3 * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com
5 * SPDX-License-Identifier: GPL-2.0+
13 #include <fdt_support.h>
18 #include <fsl_esdhc.h>
20 #include <asm/fsl_serdes.h>
21 #include <asm/fsl_mpc83xx_serdes.h>
23 DECLARE_GLOBAL_DATA_PTR;
26 * The following are used to control the SPI chip selects for the SPI command.
28 #ifdef CONFIG_MPC8XXX_SPI
30 #define SPI_CS_MASK 0x00400000
32 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
34 return bus == 0 && cs == 0;
37 void spi_cs_activate(struct spi_slave *slave)
39 immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
42 clrbits_be32(&immr->gpio[0].dat, SPI_CS_MASK);
45 void spi_cs_deactivate(struct spi_slave *slave)
47 immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
50 setbits_be32(&immr->gpio[0].dat, SPI_CS_MASK);
52 #endif /* CONFIG_MPC8XXX_SPI */
54 #ifdef CONFIG_FSL_ESDHC
55 int board_mmc_init(bd_t *bd)
57 return fsl_esdhc_mmc_init(bd);
61 static u8 read_board_info(void)
66 if (i2c_read(CONFIG_SYS_I2C_PCF8574A_ADDR, 0, 0, &val8, 1) == 0)
74 static const char * const rev_str[] = {
84 info = read_board_info();
85 i = (!info) ? 4 : info & 0x03;
87 printf("Board: Freescale MPC8308RDB Rev %s\n", rev_str[i]);
92 static struct pci_region pcie_regions_0[] = {
94 .bus_start = CONFIG_SYS_PCIE1_MEM_BASE,
95 .phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
96 .size = CONFIG_SYS_PCIE1_MEM_SIZE,
97 .flags = PCI_REGION_MEM,
100 .bus_start = CONFIG_SYS_PCIE1_IO_BASE,
101 .phys_start = CONFIG_SYS_PCIE1_IO_PHYS,
102 .size = CONFIG_SYS_PCIE1_IO_SIZE,
103 .flags = PCI_REGION_IO,
107 void pci_init_board(void)
109 immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
110 sysconf83xx_t *sysconf = &immr->sysconf;
111 law83xx_t *pcie_law = sysconf->pcielaw;
112 struct pci_region *pcie_reg[] = { pcie_regions_0 };
114 fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_PEX,
115 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
117 /* Deassert the resets in the control register */
118 out_be32(&sysconf->pecr1, 0xE0008000);
121 /* Configure PCI Express Local Access Windows */
122 out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);
123 out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
125 mpc83xx_pcie_init(1, pcie_reg);
128 * Miscellaneous late-boot configurations
130 * If a VSC7385 microcode image is present, then upload it.
132 int misc_init_r(void)
134 #ifdef CONFIG_MPC8XXX_SPI
135 immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
136 sysconf83xx_t *sysconf = &immr->sysconf;
139 * Set proper bits in SICRH to allow SPI on header J8
141 * NOTE: this breaks the TSEC2 interface, attached to the Vitesse
142 * switch. The pinmux configuration does not have a fine enough
143 * granularity to support both simultaneously.
145 clrsetbits_be32(&sysconf->sicrh, SICRH_GPIO_A_TSEC2, SICRH_GPIO_A_GPIO);
146 puts("WARNING: SPI enabled, TSEC2 support is broken\n");
148 /* Set header J8 SPI chip select output, disabled */
149 setbits_be32(&immr->gpio[0].dir, SPI_CS_MASK);
150 setbits_be32(&immr->gpio[0].dat, SPI_CS_MASK);
153 #ifdef CONFIG_VSC7385_IMAGE
154 if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE,
155 CONFIG_VSC7385_IMAGE_SIZE)) {
156 puts("Failure uploading VSC7385 microcode.\n");
163 #if defined(CONFIG_OF_BOARD_SETUP)
164 void ft_board_setup(void *blob, bd_t *bd)
166 ft_cpu_setup(blob, bd);
167 fdt_fixup_dr_usb(blob, bd);
168 fdt_fixup_esdhc(blob, bd);
172 int board_eth_init(bd_t *bis)
176 /* Initialize TSECs first */
177 rv = cpu_eth_init(bis);
181 printf("ERROR: failed to initialize TSECs.\n");
183 rv = pci_eth_init(bis);
187 printf("ERROR: failed to initialize PCI Ethernet.\n");