2 * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
14 * PCI Configuration space access support for MPC83xx PCI Bridge
22 #include <asm/fsl_i2c.h>
23 #include "../common/pq-mds-pib.h"
25 DECLARE_GLOBAL_DATA_PTR;
27 static struct pci_region pci1_regions[] = {
29 bus_start: CONFIG_SYS_PCI1_MEM_BASE,
30 phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
31 size: CONFIG_SYS_PCI1_MEM_SIZE,
32 flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
35 bus_start: CONFIG_SYS_PCI1_IO_BASE,
36 phys_start: CONFIG_SYS_PCI1_IO_PHYS,
37 size: CONFIG_SYS_PCI1_IO_SIZE,
41 bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
42 phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
43 size: CONFIG_SYS_PCI1_MMIO_SIZE,
48 #ifdef CONFIG_MPC83XX_PCI2
49 static struct pci_region pci2_regions[] = {
51 bus_start: CONFIG_SYS_PCI2_MEM_BASE,
52 phys_start: CONFIG_SYS_PCI2_MEM_PHYS,
53 size: CONFIG_SYS_PCI2_MEM_SIZE,
54 flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
57 bus_start: CONFIG_SYS_PCI2_IO_BASE,
58 phys_start: CONFIG_SYS_PCI2_IO_PHYS,
59 size: CONFIG_SYS_PCI2_IO_SIZE,
63 bus_start: CONFIG_SYS_PCI2_MMIO_BASE,
64 phys_start: CONFIG_SYS_PCI2_MMIO_PHYS,
65 size: CONFIG_SYS_PCI2_MMIO_SIZE,
71 DECLARE_GLOBAL_DATA_PTR;
74 void pci_init_board(void)
75 #ifdef CONFIG_PCISLAVE
77 volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
78 volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
79 volatile pcictrl83xx_t *pci_ctrl = &immr->pci_ctrl[0];
80 struct pci_region *reg[] = { pci1_regions };
82 /* Configure PCI Local Access Windows */
83 pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
84 pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
86 pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
87 pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M;
89 mpc83xx_pci_init(1, reg, 0);
92 * Configure PCI Inbound Translation Windows
94 pci_ctrl[0].pitar0 = 0x0;
95 pci_ctrl[0].pibar0 = 0x0;
96 pci_ctrl[0].piwar0 = PIWAR_EN | PIWAR_RTT_SNOOP |
97 PIWAR_WTT_SNOOP | PIWAR_IWS_4K;
99 pci_ctrl[0].pitar1 = 0x0;
100 pci_ctrl[0].pibar1 = 0x0;
101 pci_ctrl[0].piebar1 = 0x0;
102 pci_ctrl[0].piwar1 &= ~PIWAR_EN;
104 pci_ctrl[0].pitar2 = 0x0;
105 pci_ctrl[0].pibar2 = 0x0;
106 pci_ctrl[0].piebar2 = 0x0;
107 pci_ctrl[0].piwar2 &= ~PIWAR_EN;
109 /* Unlock the configuration bit */
110 mpc83xx_pcislave_unlock(0);
111 printf("PCI: Agent mode enabled\n");
115 volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
116 volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
117 volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
118 #ifndef CONFIG_MPC83XX_PCI2
119 struct pci_region *reg[] = { pci1_regions };
121 struct pci_region *reg[] = { pci1_regions, pci2_regions };
124 /* initialize the PCA9555PW IO expander on the PIB board */
128 clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2;
129 printf("PCI clock is 66MHz\n");
130 #elif defined(PCI_33M)
131 clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2 |
132 OCCR_PCICD0 | OCCR_PCICD1 | OCCR_PCICD2 | OCCR_PCICR;
133 printf("PCI clock is 33MHz\n");
135 clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2;
136 printf("PCI clock is 66MHz\n");
140 /* Configure PCI Local Access Windows */
141 pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
142 pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_512M;
144 pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
145 pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_1M;
149 #ifndef CONFIG_MPC83XX_PCI2
150 mpc83xx_pci_init(1, reg, 0);
152 mpc83xx_pci_init(2, reg, 0);
155 #endif /* CONFIG_PCISLAVE */