1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2011 Freescale Semiconductor, Inc.
8 #include <fsl_ddr_sdram.h>
9 #include <fsl_ddr_dimm_params.h>
11 struct board_specific_parameters {
13 u32 datarate_mhz_high;
21 * This table contains all valid speeds we want to override with board
22 * specific parameters. datarate_mhz_high values need to be in ascending order
23 * for each n_ranks group.
25 static const struct board_specific_parameters udimm0[] = {
28 * num| hi| clk| cpo|wrdata|2T
29 * ranks| mhz|adjst| | delay|
34 {2, 850, 4, 31, 2, 0},
38 {1, 850, 4, 31, 2, 0},
42 void fsl_ddr_board_options(memctl_options_t *popts,
44 unsigned int ctrl_num)
46 const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
50 if (ctrl_num != 0) /* we have only one controller */
52 for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
56 if (i >= CONFIG_DIMM_SLOTS_PER_CTLR) /* no DIMM */
61 /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
62 * freqency and n_banks specified in board_specific_parameters table.
64 ddr_freq = get_ddr_freq(0) / 1000000;
65 while (pbsp->datarate_mhz_high) {
66 if (pbsp->n_ranks == pdimm[i].n_ranks) {
67 if (ddr_freq <= pbsp->datarate_mhz_high) {
68 popts->clk_adjust = pbsp->clk_adjust;
69 popts->cpo_override = pbsp->cpo;
70 popts->write_data_delay =
71 pbsp->write_data_delay;
72 popts->twot_en = pbsp->force_2t;
81 printf("Error: board specific timing not found "
82 "for data rate %lu MT/s!\n"
83 "Trying to use the highest speed (%u) parameters\n",
84 ddr_freq, pbsp_highest->datarate_mhz_high);
85 popts->clk_adjust = pbsp_highest->clk_adjust;
86 popts->cpo_override = pbsp_highest->cpo;
87 popts->write_data_delay = pbsp_highest->write_data_delay;
88 popts->twot_en = pbsp_highest->force_2t;
90 panic("DIMM is not supported by this board");
95 * Factors to consider for half-strength driver enable:
96 * - number of DIMMs installed
98 popts->half_strength_driver_enable = 0;
99 popts->dqs_config = 0; /* only true DQS signal is used on board */