2 * Copyright 2011 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
9 #include <fsl_ddr_sdram.h>
10 #include <fsl_ddr_dimm_params.h>
12 struct board_specific_parameters {
14 u32 datarate_mhz_high;
22 * This table contains all valid speeds we want to override with board
23 * specific parameters. datarate_mhz_high values need to be in ascending order
24 * for each n_ranks group.
26 static const struct board_specific_parameters udimm0[] = {
29 * num| hi| clk| cpo|wrdata|2T
30 * ranks| mhz|adjst| | delay|
35 {2, 850, 4, 31, 2, 0},
39 {1, 850, 4, 31, 2, 0},
43 void fsl_ddr_board_options(memctl_options_t *popts,
45 unsigned int ctrl_num)
47 const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
51 if (ctrl_num != 0) /* we have only one controller */
53 for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
57 if (i >= CONFIG_DIMM_SLOTS_PER_CTLR) /* no DIMM */
62 /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
63 * freqency and n_banks specified in board_specific_parameters table.
65 ddr_freq = get_ddr_freq(0) / 1000000;
66 while (pbsp->datarate_mhz_high) {
67 if (pbsp->n_ranks == pdimm[i].n_ranks) {
68 if (ddr_freq <= pbsp->datarate_mhz_high) {
69 popts->clk_adjust = pbsp->clk_adjust;
70 popts->cpo_override = pbsp->cpo;
71 popts->write_data_delay =
72 pbsp->write_data_delay;
73 popts->twot_en = pbsp->force_2t;
82 printf("Error: board specific timing not found "
83 "for data rate %lu MT/s!\n"
84 "Trying to use the highest speed (%u) parameters\n",
85 ddr_freq, pbsp_highest->datarate_mhz_high);
86 popts->clk_adjust = pbsp_highest->clk_adjust;
87 popts->cpo_override = pbsp_highest->cpo;
88 popts->write_data_delay = pbsp_highest->write_data_delay;
89 popts->twot_en = pbsp_highest->force_2t;
91 panic("DIMM is not supported by this board");
96 * Factors to consider for half-strength driver enable:
97 * - number of DIMMs installed
99 popts->half_strength_driver_enable = 0;
100 popts->dqs_config = 0; /* only true DQS signal is used on board */