1 // SPDX-License-Identifier: GPL-2.0+
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
10 #include <asm/mpc8349_pci.h>
14 #ifdef CONFIG_SYS_FSL_DDR2
15 #include <fsl_ddr_sdram.h>
17 #include <spd_sdram.h>
20 #if defined(CONFIG_OF_LIBFDT)
21 #include <linux/libfdt.h>
24 DECLARE_GLOBAL_DATA_PTR;
26 int fixed_sdram(void);
27 void sdram_init(void);
29 #if defined(CONFIG_DDR_ECC) && defined(CONFIG_MPC83xx)
30 void ddr_enable_ecc(unsigned int dram_size);
33 int board_early_init_f (void)
35 volatile u8* bcsr = (volatile u8*)CONFIG_SYS_BCSR;
37 /* Enable flash write */
40 #ifdef CONFIG_SYS_USE_MPC834XSYS_USB_PHY
41 /* Use USB PHY on SYS board */
48 #define ns2clk(ns) (ns / (1000000000 / CONFIG_8349_CLKIN) + 1)
52 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
53 phys_size_t msize = 0;
55 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
58 /* DDR SDRAM - Main SODIMM */
59 im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
60 #if defined(CONFIG_SPD_EEPROM)
61 #ifndef CONFIG_SYS_FSL_DDR2
62 msize = spd_sdram() * 1024 * 1024;
63 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
64 ddr_enable_ecc(msize);
67 msize = fsl_ddr_sdram();
70 msize = fixed_sdram() * 1024 * 1024;
73 * Initialize SDRAM if it is on local bus.
77 /* set total bus SDRAM size(bytes) -- DDR */
83 #if !defined(CONFIG_SPD_EEPROM)
84 /*************************************************************************
85 * fixed sdram init -- doesn't use serial presence detect.
86 ************************************************************************/
89 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
90 u32 msize = CONFIG_SYS_DDR_SIZE;
91 u32 ddr_size = msize << 20; /* DDR size in bytes */
92 u32 ddr_size_log2 = __ilog2(ddr_size);
94 im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
95 im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
97 #if (CONFIG_SYS_DDR_SIZE != 256)
98 #warning Currenly any ddr size other than 256 is not supported
101 im->ddr.csbnds[2].csbnds = CONFIG_SYS_DDR_CS2_BNDS;
102 im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS2_CONFIG;
103 im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
104 im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
105 im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
106 im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
107 im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
108 im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
109 im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
110 im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
111 im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
112 im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
115 #if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0)
116 #warning Chip select bounds is only configurable in 16MB increments
118 im->ddr.csbnds[2].csbnds =
119 ((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
120 (((CONFIG_SYS_DDR_SDRAM_BASE + ddr_size - 1) >>
121 CSBNDS_EA_SHIFT) & CSBNDS_EA);
122 im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS2_CONFIG;
124 /* currently we use only one CS, so disable the other banks */
125 im->ddr.cs_config[0] = 0;
126 im->ddr.cs_config[1] = 0;
127 im->ddr.cs_config[3] = 0;
129 im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
130 im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
134 #if defined(CONFIG_DDR_2T_TIMING)
137 | 2 << SDRAM_CFG_SDRAM_TYPE_SHIFT;
138 #if defined (CONFIG_DDR_32BIT)
139 /* for 32-bit mode burst length is 8 */
140 im->ddr.sdram_cfg |= (SDRAM_CFG_32_BE | SDRAM_CFG_8_BE);
142 im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
144 im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
148 /* enable DDR controller */
149 im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
152 #endif/*!CONFIG_SYS_SPD_EEPROM*/
155 int checkboard (void)
158 * Warning: do not read the BCSR registers here
160 * There is a timing bug in the 8349E and 8349EA BCSR code
161 * version 1.2 (read from BCSR 11) that will cause the CFI
162 * flash initialization code to overwrite BCSR 0, disabling
163 * the serial ports and gigabit ethernet
166 puts("Board: Freescale MPC8349EMDS\n");
171 * if MPC8349EMDS is soldered with SDRAM
173 #if defined(CONFIG_SYS_BR2_PRELIM) \
174 && defined(CONFIG_SYS_OR2_PRELIM) \
175 && defined(CONFIG_SYS_LBLAWBAR2_PRELIM) \
176 && defined(CONFIG_SYS_LBLAWAR2_PRELIM)
178 * Initialize SDRAM memory on the Local Bus.
181 void sdram_init(void)
183 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
184 volatile fsl_lbc_t *lbc = &immap->im_lbc;
185 uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
188 * Setup SDRAM Base and Option Registers, already done in cpu_init.c
191 /* setup mtrpt, lsrt and lbcr for LB bus */
192 lbc->lbcr = CONFIG_SYS_LBC_LBCR;
193 lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
194 lbc->lsrt = CONFIG_SYS_LBC_LSRT;
198 * Configure the SDRAM controller Machine Mode Register.
200 lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* 0x40636733; normal operation */
202 lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1; /* 0x68636733; precharge all the banks */
207 lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2; /* 0x48636733; auto refresh */
234 /* 0x58636733; mode register write operation */
235 lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4;
240 lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* 0x40636733; normal operation */
246 void sdram_init(void)
252 * The following are used to control the SPI chip selects for the SPI command.
254 #ifdef CONFIG_MPC8XXX_SPI
256 #define SPI_CS_MASK 0x80000000
258 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
260 return bus == 0 && cs == 0;
263 void spi_cs_activate(struct spi_slave *slave)
265 volatile gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0];
267 iopd->dat &= ~SPI_CS_MASK;
270 void spi_cs_deactivate(struct spi_slave *slave)
272 volatile gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0];
274 iopd->dat |= SPI_CS_MASK;
276 #endif /* CONFIG_HARD_SPI */
278 #if defined(CONFIG_OF_BOARD_SETUP)
279 int ft_board_setup(void *blob, bd_t *bd)
281 ft_cpu_setup(blob, bd);
283 ft_pci_setup(blob, bd);