3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #include <asm/mpc8349_pci.h>
32 #ifdef CONFIG_FSL_DDR2
33 #include <asm/fsl_ddr_sdram.h>
35 #include <spd_sdram.h>
38 #if defined(CONFIG_OF_LIBFDT)
42 int fixed_sdram(void);
43 void sdram_init(void);
45 #if defined(CONFIG_DDR_ECC) && defined(CONFIG_MPC83xx)
46 void ddr_enable_ecc(unsigned int dram_size);
49 int board_early_init_f (void)
51 volatile u8* bcsr = (volatile u8*)CONFIG_SYS_BCSR;
53 /* Enable flash write */
56 #ifdef CONFIG_SYS_USE_MPC834XSYS_USB_PHY
57 /* Use USB PHY on SYS board */
64 #define ns2clk(ns) (ns / (1000000000 / CONFIG_8349_CLKIN) + 1)
66 phys_size_t initdram (int board_type)
68 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
69 phys_size_t msize = 0;
71 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
74 /* DDR SDRAM - Main SODIMM */
75 im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
76 #if defined(CONFIG_SPD_EEPROM)
77 #ifndef CONFIG_FSL_DDR2
78 msize = spd_sdram() * 1024 * 1024;
79 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
80 ddr_enable_ecc(msize);
83 msize = fsl_ddr_sdram();
86 msize = fixed_sdram() * 1024 * 1024;
89 * Initialize SDRAM if it is on local bus.
93 /* return total bus SDRAM size(bytes) -- DDR */
97 #if !defined(CONFIG_SPD_EEPROM)
98 /*************************************************************************
99 * fixed sdram init -- doesn't use serial presence detect.
100 ************************************************************************/
101 int fixed_sdram(void)
103 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
104 u32 msize = CONFIG_SYS_DDR_SIZE;
105 u32 ddr_size = msize << 20; /* DDR size in bytes */
106 u32 ddr_size_log2 = __ilog2(ddr_size);
108 im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
109 im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
111 #if (CONFIG_SYS_DDR_SIZE != 256)
112 #warning Currenly any ddr size other than 256 is not supported
115 im->ddr.csbnds[2].csbnds = CONFIG_SYS_DDR_CS2_BNDS;
116 im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS2_CONFIG;
117 im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
118 im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
119 im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
120 im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
121 im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
122 im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
123 im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
124 im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
125 im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
126 im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
129 #if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0)
130 #warning Chip select bounds is only configurable in 16MB increments
132 im->ddr.csbnds[2].csbnds =
133 ((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
134 (((CONFIG_SYS_DDR_SDRAM_BASE + ddr_size - 1) >>
135 CSBNDS_EA_SHIFT) & CSBNDS_EA);
136 im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS2_CONFIG;
138 /* currently we use only one CS, so disable the other banks */
139 im->ddr.cs_config[0] = 0;
140 im->ddr.cs_config[1] = 0;
141 im->ddr.cs_config[3] = 0;
143 im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
144 im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
148 #if defined(CONFIG_DDR_2T_TIMING)
151 | 2 << SDRAM_CFG_SDRAM_TYPE_SHIFT;
152 #if defined (CONFIG_DDR_32BIT)
153 /* for 32-bit mode burst length is 8 */
154 im->ddr.sdram_cfg |= (SDRAM_CFG_32_BE | SDRAM_CFG_8_BE);
156 im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
158 im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
162 /* enable DDR controller */
163 im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
166 #endif/*!CONFIG_SYS_SPD_EEPROM*/
169 int checkboard (void)
172 * Warning: do not read the BCSR registers here
174 * There is a timing bug in the 8349E and 8349EA BCSR code
175 * version 1.2 (read from BCSR 11) that will cause the CFI
176 * flash initialization code to overwrite BCSR 0, disabling
177 * the serial ports and gigabit ethernet
180 puts("Board: Freescale MPC8349EMDS\n");
185 * if MPC8349EMDS is soldered with SDRAM
187 #if defined(CONFIG_SYS_BR2_PRELIM) \
188 && defined(CONFIG_SYS_OR2_PRELIM) \
189 && defined(CONFIG_SYS_LBLAWBAR2_PRELIM) \
190 && defined(CONFIG_SYS_LBLAWAR2_PRELIM)
192 * Initialize SDRAM memory on the Local Bus.
195 void sdram_init(void)
197 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
198 volatile fsl_lbc_t *lbc = &immap->im_lbc;
199 uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
202 * Setup SDRAM Base and Option Registers, already done in cpu_init.c
205 /* setup mtrpt, lsrt and lbcr for LB bus */
206 lbc->lbcr = CONFIG_SYS_LBC_LBCR;
207 lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
208 lbc->lsrt = CONFIG_SYS_LBC_LSRT;
212 * Configure the SDRAM controller Machine Mode Register.
214 lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* 0x40636733; normal operation */
216 lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1; /* 0x68636733; precharge all the banks */
221 lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2; /* 0x48636733; auto refresh */
248 /* 0x58636733; mode register write operation */
249 lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4;
254 lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* 0x40636733; normal operation */
260 void sdram_init(void)
266 * The following are used to control the SPI chip selects for the SPI command.
268 #ifdef CONFIG_MPC8XXX_SPI
270 #define SPI_CS_MASK 0x80000000
272 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
274 return bus == 0 && cs == 0;
277 void spi_cs_activate(struct spi_slave *slave)
279 volatile gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0];
281 iopd->dat &= ~SPI_CS_MASK;
284 void spi_cs_deactivate(struct spi_slave *slave)
286 volatile gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0];
288 iopd->dat |= SPI_CS_MASK;
290 #endif /* CONFIG_HARD_SPI */
292 #if defined(CONFIG_OF_BOARD_SETUP)
293 void ft_board_setup(void *blob, bd_t *bd)
295 ft_cpu_setup(blob, bd);
297 ft_pci_setup(blob, bd);