2 * See file CREDITS for list of people who contributed to this
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 #include <asm/global_data.h>
26 #include <asm/mpc8349_pci.h>
28 #if defined(CONFIG_OF_LIBFDT)
30 #include <fdt_support.h>
34 DECLARE_GLOBAL_DATA_PTR;
38 /* System RAM mapped to PCI space */
39 #define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE
40 #define CONFIG_PCI_SYS_MEM_PHYS CFG_SDRAM_BASE
42 #ifndef CONFIG_PCI_PNP
43 static struct pci_config_table pci_mpc8349emds_config_table[] = {
44 {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
45 PCI_IDSEL_NUMBER, PCI_ANY_ID,
46 pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
48 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
55 static struct pci_controller pci_hose[] = {
57 #ifndef CONFIG_PCI_PNP
58 config_table:pci_mpc8349emds_config_table,
62 #ifndef CONFIG_PCI_PNP
63 config_table:pci_mpc8349emds_config_table,
68 /**************************************************************************
70 * pib_init() -- initialize the PCA9555PW IO expander on the PIB board
76 u8 val8, orig_i2c_bus;
78 * Assign PIB PMC slot to desired PCI bus
80 /* Switch temporarily to I2C bus #2 */
81 orig_i2c_bus = i2c_get_bus_num();
85 i2c_write(0x23, 0x6, 1, &val8, 1);
86 i2c_write(0x23, 0x7, 1, &val8, 1);
88 i2c_write(0x23, 0x2, 1, &val8, 1);
89 i2c_write(0x23, 0x3, 1, &val8, 1);
92 i2c_write(0x26, 0x6, 1, &val8, 1);
94 i2c_write(0x26, 0x7, 1, &val8, 1);
95 #if defined(PCI_64BIT)
96 val8 = 0xf4; /* PMC2:PCI1/64-bit */
97 #elif defined(PCI_ALL_PCI1)
98 val8 = 0xf3; /* PMC1:PCI1 PMC2:PCI1 PMC3:PCI1 */
99 #elif defined(PCI_ONE_PCI1)
100 val8 = 0xf9; /* PMC1:PCI1 PMC2:PCI2 PMC3:PCI2 */
102 val8 = 0xf5; /* PMC1:PCI1 PMC2:PCI1 PMC3:PCI2 */
104 i2c_write(0x26, 0x2, 1, &val8, 1);
106 i2c_write(0x26, 0x3, 1, &val8, 1);
108 i2c_write(0x27, 0x6, 1, &val8, 1);
109 i2c_write(0x27, 0x7, 1, &val8, 1);
111 i2c_write(0x27, 0x2, 1, &val8, 1);
113 i2c_write(0x27, 0x3, 1, &val8, 1);
116 #if defined(PCI_64BIT)
117 printf("PCI1: 64-bit on PMC2\n");
118 #elif defined(PCI_ALL_PCI1)
119 printf("PCI1: 32-bit on PMC1, PMC2, PMC3\n");
120 #elif defined(PCI_ONE_PCI1)
121 printf("PCI1: 32-bit on PMC1\n");
122 printf("PCI2: 32-bit on PMC2, PMC3\n");
124 printf("PCI1: 32-bit on PMC1, PMC2\n");
125 printf("PCI2: 32-bit on PMC3\n");
127 /* Reset to original I2C bus */
128 i2c_set_bus_num(orig_i2c_bus);
131 /**************************************************************************
134 * NOTICE: PCI2 is not currently supported
140 volatile immap_t * immr;
141 volatile clk83xx_t * clk;
142 volatile law83xx_t * pci_law;
143 volatile pot83xx_t * pci_pot;
144 volatile pcictrl83xx_t * pci_ctrl;
145 volatile pciconf83xx_t * pci_conf;
149 struct pci_controller * hose;
151 immr = (immap_t *)CFG_IMMR;
152 clk = (clk83xx_t *)&immr->clk;
153 pci_law = immr->sysconf.pcilaw;
154 pci_pot = immr->ios.pot;
155 pci_ctrl = immr->pci_ctrl;
156 pci_conf = immr->pci_conf;
163 * Configure PCI controller and PCI_CLK_OUTPUT both in 66M mode
168 clk->occr = 0xff000000;
172 * Release PCI RST Output signal
178 #ifdef CONFIG_MPC83XX_PCI2
184 /* We need to wait at least a 1sec based on PCI specs */
188 for (i = 0; i < 1000; ++i)
193 * Configure PCI Local Access Windows
195 pci_law[0].bar = CFG_PCI1_MEM_PHYS & LAWBAR_BAR;
196 pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
198 pci_law[1].bar = CFG_PCI1_IO_PHYS & LAWBAR_BAR;
199 pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M;
202 * Configure PCI Outbound Translation Windows
205 /* PCI1 mem space - prefetch */
206 pci_pot[0].potar = (CFG_PCI1_MEM_BASE >> 12) & POTAR_TA_MASK;
207 pci_pot[0].pobar = (CFG_PCI1_MEM_PHYS >> 12) & POBAR_BA_MASK;
208 pci_pot[0].pocmr = POCMR_EN | POCMR_PREFETCH_EN | (POCMR_CM_256M & POCMR_CM_MASK);
211 pci_pot[1].potar = (CFG_PCI1_IO_BASE >> 12) & POTAR_TA_MASK;
212 pci_pot[1].pobar = (CFG_PCI1_IO_PHYS >> 12) & POBAR_BA_MASK;
213 pci_pot[1].pocmr = POCMR_EN | POCMR_IO | (POCMR_CM_1M & POCMR_CM_MASK);
215 /* PCI1 mmio - non-prefetch mem space */
216 pci_pot[2].potar = (CFG_PCI1_MMIO_BASE >> 12) & POTAR_TA_MASK;
217 pci_pot[2].pobar = (CFG_PCI1_MMIO_PHYS >> 12) & POBAR_BA_MASK;
218 pci_pot[2].pocmr = POCMR_EN | (POCMR_CM_256M & POCMR_CM_MASK);
221 * Configure PCI Inbound Translation Windows
224 /* we need RAM mapped to PCI space for the devices to
225 * access main memory */
226 pci_ctrl[0].pitar1 = 0x0;
227 pci_ctrl[0].pibar1 = 0x0;
228 pci_ctrl[0].piebar1 = 0x0;
229 pci_ctrl[0].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size) - 1);
231 hose->first_busno = 0;
232 hose->last_busno = 0xff;
234 /* PCI memory prefetch space */
235 pci_set_region(hose->regions + 0,
239 PCI_REGION_MEM|PCI_REGION_PREFETCH);
241 /* PCI memory space */
242 pci_set_region(hose->regions + 1,
249 pci_set_region(hose->regions + 2,
255 /* System memory space */
256 pci_set_region(hose->regions + 3,
257 CONFIG_PCI_SYS_MEM_BUS,
258 CONFIG_PCI_SYS_MEM_PHYS,
260 PCI_REGION_MEM | PCI_REGION_MEMORY);
262 hose->region_count = 4;
264 pci_setup_indirect(hose,
268 pci_register_hose(hose);
271 * Write to Command register
274 dev = PCI_BDF(hose->first_busno, 0, 0);
275 pci_hose_read_config_word (hose, dev, PCI_COMMAND, ®16);
276 reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
277 pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);
280 * Clear non-reserved bits in status register.
282 pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
283 pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
284 pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
286 #ifdef CONFIG_PCI_SCAN_SHOW
287 printf("PCI: Bus Dev VenId DevId Class Int\n");
292 hose->last_busno = pci_hose_scan(hose);
294 #ifdef CONFIG_MPC83XX_PCI2
298 * Configure PCI Outbound Translation Windows
301 /* PCI2 mem space - prefetch */
302 pci_pot[3].potar = (CFG_PCI2_MEM_BASE >> 12) & POTAR_TA_MASK;
303 pci_pot[3].pobar = (CFG_PCI2_MEM_PHYS >> 12) & POBAR_BA_MASK;
304 pci_pot[3].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_PREFETCH_EN | (POCMR_CM_256M & POCMR_CM_MASK);
307 pci_pot[4].potar = (CFG_PCI2_IO_BASE >> 12) & POTAR_TA_MASK;
308 pci_pot[4].pobar = (CFG_PCI2_IO_PHYS >> 12) & POBAR_BA_MASK;
309 pci_pot[4].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_IO | (POCMR_CM_1M & POCMR_CM_MASK);
311 /* PCI2 mmio - non-prefetch mem space */
312 pci_pot[5].potar = (CFG_PCI2_MMIO_BASE >> 12) & POTAR_TA_MASK;
313 pci_pot[5].pobar = (CFG_PCI2_MMIO_PHYS >> 12) & POBAR_BA_MASK;
314 pci_pot[5].pocmr = POCMR_EN | POCMR_PCI2 | (POCMR_CM_256M & POCMR_CM_MASK);
317 * Configure PCI Inbound Translation Windows
320 /* we need RAM mapped to PCI space for the devices to
321 * access main memory */
322 pci_ctrl[1].pitar1 = 0x0;
323 pci_ctrl[1].pibar1 = 0x0;
324 pci_ctrl[1].piebar1 = 0x0;
325 pci_ctrl[1].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size) - 1);
327 hose->first_busno = pci_hose[0].last_busno + 1;
328 hose->last_busno = 0xff;
330 /* PCI memory prefetch space */
331 pci_set_region(hose->regions + 0,
335 PCI_REGION_MEM|PCI_REGION_PREFETCH);
337 /* PCI memory space */
338 pci_set_region(hose->regions + 1,
345 pci_set_region(hose->regions + 2,
351 /* System memory space */
352 pci_set_region(hose->regions + 3,
353 CONFIG_PCI_SYS_MEM_BUS,
354 CONFIG_PCI_SYS_MEM_PHYS,
356 PCI_REGION_MEM | PCI_REGION_MEMORY);
358 hose->region_count = 4;
360 pci_setup_indirect(hose,
364 pci_register_hose(hose);
367 * Write to Command register
370 dev = PCI_BDF(hose->first_busno, 0, 0);
371 pci_hose_read_config_word (hose, dev, PCI_COMMAND, ®16);
372 reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
373 pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);
376 * Clear non-reserved bits in status register.
378 pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
379 pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
380 pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
385 hose->last_busno = pci_hose_scan(hose);
390 #if defined(CONFIG_OF_LIBFDT)
391 void ft_pci_setup(void *blob, bd_t *bd)
397 nodeoffset = fdt_path_offset(blob, "/aliases");
398 if (nodeoffset >= 0) {
399 path = fdt_getprop(blob, nodeoffset, "pci0", NULL);
401 tmp[0] = cpu_to_be32(pci_hose[0].first_busno);
402 tmp[1] = cpu_to_be32(pci_hose[0].last_busno);
403 do_fixup_by_path(blob, path, "bus-range",
404 &tmp, sizeof(tmp), 1);
406 tmp[0] = cpu_to_be32(gd->pci_clk);
407 do_fixup_by_path(blob, path, "clock-frequency",
408 &tmp, sizeof(tmp[0]), 1);
410 #ifdef CONFIG_MPC83XX_PCI2
411 path = fdt_getprop(blob, nodeoffset, "pci1", NULL);
413 tmp[0] = cpu_to_be32(pci_hose[0].first_busno);
414 tmp[1] = cpu_to_be32(pci_hose[0].last_busno);
415 do_fixup_by_path(blob, path, "bus-range",
416 &tmp, sizeof(tmp), 1);
418 tmp[0] = cpu_to_be32(gd->pci_clk);
419 do_fixup_by_path(blob, path, "clock-frequency",
420 &tmp, sizeof(tmp[0]), 1);
425 #endif /* CONFIG_OF_LIBFDT */
426 #endif /* CONFIG_PCI */