2 * See file CREDITS for list of people who contributed to this
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 #include <asm/global_data.h>
26 #include <asm/mpc8349_pci.h>
28 #if defined(CONFIG_OF_FLAT_TREE)
30 #elif defined(CONFIG_OF_LIBFDT)
32 #include <fdt_support.h>
36 DECLARE_GLOBAL_DATA_PTR;
40 /* System RAM mapped to PCI space */
41 #define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE
42 #define CONFIG_PCI_SYS_MEM_PHYS CFG_SDRAM_BASE
44 #ifndef CONFIG_PCI_PNP
45 static struct pci_config_table pci_mpc8349emds_config_table[] = {
46 {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
47 PCI_IDSEL_NUMBER, PCI_ANY_ID,
48 pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
50 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
57 static struct pci_controller pci_hose[] = {
59 #ifndef CONFIG_PCI_PNP
60 config_table:pci_mpc8349emds_config_table,
64 #ifndef CONFIG_PCI_PNP
65 config_table:pci_mpc8349emds_config_table,
70 /**************************************************************************
72 * pib_init() -- initialize the PCA9555PW IO expander on the PIB board
78 u8 val8, orig_i2c_bus;
80 * Assign PIB PMC slot to desired PCI bus
82 /* Switch temporarily to I2C bus #2 */
83 orig_i2c_bus = i2c_get_bus_num();
87 i2c_write(0x23, 0x6, 1, &val8, 1);
88 i2c_write(0x23, 0x7, 1, &val8, 1);
90 i2c_write(0x23, 0x2, 1, &val8, 1);
91 i2c_write(0x23, 0x3, 1, &val8, 1);
94 i2c_write(0x26, 0x6, 1, &val8, 1);
96 i2c_write(0x26, 0x7, 1, &val8, 1);
97 #if defined(PCI_64BIT)
98 val8 = 0xf4; /* PMC2:PCI1/64-bit */
99 #elif defined(PCI_ALL_PCI1)
100 val8 = 0xf3; /* PMC1:PCI1 PMC2:PCI1 PMC3:PCI1 */
101 #elif defined(PCI_ONE_PCI1)
102 val8 = 0xf9; /* PMC1:PCI1 PMC2:PCI2 PMC3:PCI2 */
104 val8 = 0xf5; /* PMC1:PCI1 PMC2:PCI1 PMC3:PCI2 */
106 i2c_write(0x26, 0x2, 1, &val8, 1);
108 i2c_write(0x26, 0x3, 1, &val8, 1);
110 i2c_write(0x27, 0x6, 1, &val8, 1);
111 i2c_write(0x27, 0x7, 1, &val8, 1);
113 i2c_write(0x27, 0x2, 1, &val8, 1);
115 i2c_write(0x27, 0x3, 1, &val8, 1);
118 #if defined(PCI_64BIT)
119 printf("PCI1: 64-bit on PMC2\n");
120 #elif defined(PCI_ALL_PCI1)
121 printf("PCI1: 32-bit on PMC1, PMC2, PMC3\n");
122 #elif defined(PCI_ONE_PCI1)
123 printf("PCI1: 32-bit on PMC1\n");
124 printf("PCI2: 32-bit on PMC2, PMC3\n");
126 printf("PCI1: 32-bit on PMC1, PMC2\n");
127 printf("PCI2: 32-bit on PMC3\n");
129 /* Reset to original I2C bus */
130 i2c_set_bus_num(orig_i2c_bus);
133 /**************************************************************************
136 * NOTICE: PCI2 is not currently supported
142 volatile immap_t * immr;
143 volatile clk83xx_t * clk;
144 volatile law83xx_t * pci_law;
145 volatile pot83xx_t * pci_pot;
146 volatile pcictrl83xx_t * pci_ctrl;
147 volatile pciconf83xx_t * pci_conf;
151 struct pci_controller * hose;
153 immr = (immap_t *)CFG_IMMR;
154 clk = (clk83xx_t *)&immr->clk;
155 pci_law = immr->sysconf.pcilaw;
156 pci_pot = immr->ios.pot;
157 pci_ctrl = immr->pci_ctrl;
158 pci_conf = immr->pci_conf;
165 * Configure PCI controller and PCI_CLK_OUTPUT both in 66M mode
170 clk->occr = 0xff000000;
174 * Release PCI RST Output signal
180 #ifdef CONFIG_MPC83XX_PCI2
186 /* We need to wait at least a 1sec based on PCI specs */
190 for (i = 0; i < 1000; ++i)
195 * Configure PCI Local Access Windows
197 pci_law[0].bar = CFG_PCI1_MEM_PHYS & LAWBAR_BAR;
198 pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
200 pci_law[1].bar = CFG_PCI1_IO_PHYS & LAWBAR_BAR;
201 pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M;
204 * Configure PCI Outbound Translation Windows
207 /* PCI1 mem space - prefetch */
208 pci_pot[0].potar = (CFG_PCI1_MEM_BASE >> 12) & POTAR_TA_MASK;
209 pci_pot[0].pobar = (CFG_PCI1_MEM_PHYS >> 12) & POBAR_BA_MASK;
210 pci_pot[0].pocmr = POCMR_EN | POCMR_PREFETCH_EN | (POCMR_CM_256M & POCMR_CM_MASK);
213 pci_pot[1].potar = (CFG_PCI1_IO_BASE >> 12) & POTAR_TA_MASK;
214 pci_pot[1].pobar = (CFG_PCI1_IO_PHYS >> 12) & POBAR_BA_MASK;
215 pci_pot[1].pocmr = POCMR_EN | POCMR_IO | (POCMR_CM_1M & POCMR_CM_MASK);
217 /* PCI1 mmio - non-prefetch mem space */
218 pci_pot[2].potar = (CFG_PCI1_MMIO_BASE >> 12) & POTAR_TA_MASK;
219 pci_pot[2].pobar = (CFG_PCI1_MMIO_PHYS >> 12) & POBAR_BA_MASK;
220 pci_pot[2].pocmr = POCMR_EN | (POCMR_CM_256M & POCMR_CM_MASK);
223 * Configure PCI Inbound Translation Windows
226 /* we need RAM mapped to PCI space for the devices to
227 * access main memory */
228 pci_ctrl[0].pitar1 = 0x0;
229 pci_ctrl[0].pibar1 = 0x0;
230 pci_ctrl[0].piebar1 = 0x0;
231 pci_ctrl[0].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size) - 1);
233 hose->first_busno = 0;
234 hose->last_busno = 0xff;
236 /* PCI memory prefetch space */
237 pci_set_region(hose->regions + 0,
241 PCI_REGION_MEM|PCI_REGION_PREFETCH);
243 /* PCI memory space */
244 pci_set_region(hose->regions + 1,
251 pci_set_region(hose->regions + 2,
257 /* System memory space */
258 pci_set_region(hose->regions + 3,
259 CONFIG_PCI_SYS_MEM_BUS,
260 CONFIG_PCI_SYS_MEM_PHYS,
262 PCI_REGION_MEM | PCI_REGION_MEMORY);
264 hose->region_count = 4;
266 pci_setup_indirect(hose,
270 pci_register_hose(hose);
273 * Write to Command register
276 dev = PCI_BDF(hose->first_busno, 0, 0);
277 pci_hose_read_config_word (hose, dev, PCI_COMMAND, ®16);
278 reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
279 pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);
282 * Clear non-reserved bits in status register.
284 pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
285 pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
286 pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
288 #ifdef CONFIG_PCI_SCAN_SHOW
289 printf("PCI: Bus Dev VenId DevId Class Int\n");
294 hose->last_busno = pci_hose_scan(hose);
296 #ifdef CONFIG_MPC83XX_PCI2
300 * Configure PCI Outbound Translation Windows
303 /* PCI2 mem space - prefetch */
304 pci_pot[3].potar = (CFG_PCI2_MEM_BASE >> 12) & POTAR_TA_MASK;
305 pci_pot[3].pobar = (CFG_PCI2_MEM_PHYS >> 12) & POBAR_BA_MASK;
306 pci_pot[3].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_PREFETCH_EN | (POCMR_CM_256M & POCMR_CM_MASK);
309 pci_pot[4].potar = (CFG_PCI2_IO_BASE >> 12) & POTAR_TA_MASK;
310 pci_pot[4].pobar = (CFG_PCI2_IO_PHYS >> 12) & POBAR_BA_MASK;
311 pci_pot[4].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_IO | (POCMR_CM_1M & POCMR_CM_MASK);
313 /* PCI2 mmio - non-prefetch mem space */
314 pci_pot[5].potar = (CFG_PCI2_MMIO_BASE >> 12) & POTAR_TA_MASK;
315 pci_pot[5].pobar = (CFG_PCI2_MMIO_PHYS >> 12) & POBAR_BA_MASK;
316 pci_pot[5].pocmr = POCMR_EN | POCMR_PCI2 | (POCMR_CM_256M & POCMR_CM_MASK);
319 * Configure PCI Inbound Translation Windows
322 /* we need RAM mapped to PCI space for the devices to
323 * access main memory */
324 pci_ctrl[1].pitar1 = 0x0;
325 pci_ctrl[1].pibar1 = 0x0;
326 pci_ctrl[1].piebar1 = 0x0;
327 pci_ctrl[1].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size) - 1);
329 hose->first_busno = pci_hose[0].last_busno + 1;
330 hose->last_busno = 0xff;
332 /* PCI memory prefetch space */
333 pci_set_region(hose->regions + 0,
337 PCI_REGION_MEM|PCI_REGION_PREFETCH);
339 /* PCI memory space */
340 pci_set_region(hose->regions + 1,
347 pci_set_region(hose->regions + 2,
353 /* System memory space */
354 pci_set_region(hose->regions + 3,
355 CONFIG_PCI_SYS_MEM_BUS,
356 CONFIG_PCI_SYS_MEM_PHYS,
358 PCI_REGION_MEM | PCI_REGION_MEMORY);
360 hose->region_count = 4;
362 pci_setup_indirect(hose,
366 pci_register_hose(hose);
369 * Write to Command register
372 dev = PCI_BDF(hose->first_busno, 0, 0);
373 pci_hose_read_config_word (hose, dev, PCI_COMMAND, ®16);
374 reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
375 pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);
378 * Clear non-reserved bits in status register.
380 pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
381 pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
382 pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
387 hose->last_busno = pci_hose_scan(hose);
392 #if defined(CONFIG_OF_LIBFDT)
393 void ft_pci_setup(void *blob, bd_t *bd)
399 nodeoffset = fdt_path_offset(blob, "/aliases");
400 if (nodeoffset >= 0) {
401 path = fdt_getprop(blob, nodeoffset, "pci0", NULL);
403 tmp[0] = cpu_to_be32(pci_hose[0].first_busno);
404 tmp[1] = cpu_to_be32(pci_hose[0].last_busno);
405 do_fixup_by_path(blob, path, "bus-range",
406 &tmp, sizeof(tmp), 1);
408 tmp[0] = cpu_to_be32(gd->pci_clk);
409 do_fixup_by_path(blob, path, "clock-frequency",
410 &tmp, sizeof(tmp[0]), 1);
412 #ifdef CONFIG_MPC83XX_PCI2
413 path = fdt_getprop(blob, nodeoffset, "pci1", NULL);
415 tmp[0] = cpu_to_be32(pci_hose[0].first_busno);
416 tmp[1] = cpu_to_be32(pci_hose[0].last_busno);
417 do_fixup_by_path(blob, path, "bus-range",
418 &tmp, sizeof(tmp), 1);
420 tmp[0] = cpu_to_be32(gd->pci_clk);
421 do_fixup_by_path(blob, path, "clock-frequency",
422 &tmp, sizeof(tmp[0]), 1);
427 #elif defined(CONFIG_OF_FLAT_TREE)
429 ft_pci_setup(void *blob, bd_t *bd)
434 p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8500/bus-range", &len);
436 p[0] = pci_hose[0].first_busno;
437 p[1] = pci_hose[0].last_busno;
440 #ifdef CONFIG_MPC83XX_PCI2
441 p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8600/bus-range", &len);
443 p[0] = pci_hose[1].first_busno;
444 p[1] = pci_hose[1].last_busno;
448 #endif /* CONFIG_OF_FLAT_TREE */
449 #endif /* CONFIG_PCI */