2 * Copyright (C) Freescale Semiconductor, Inc. 2006.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 #include <asm/mpc8349_pci.h>
33 #include <spd_sdram.h>
35 #if defined(CONFIG_OF_LIBFDT)
39 #ifndef CONFIG_SPD_EEPROM
40 /*************************************************************************
41 * fixed sdram init -- doesn't use serial presence detect.
42 ************************************************************************/
45 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
46 /* The size of RAM, in bytes */
47 u32 ddr_size = CONFIG_SYS_DDR_SIZE << 20;
48 u32 ddr_size_log2 = __ilog2(ddr_size);
50 im->sysconf.ddrlaw[0].ar =
51 LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
52 im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
54 #if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0)
55 #warning Chip select bounds is only configurable in 16MB increments
57 im->ddr.csbnds[0].csbnds =
58 ((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
59 (((CONFIG_SYS_DDR_SDRAM_BASE + ddr_size - 1) >>
60 CSBNDS_EA_SHIFT) & CSBNDS_EA);
61 im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
63 /* Only one CS for DDR */
64 im->ddr.cs_config[1] = 0;
65 im->ddr.cs_config[2] = 0;
66 im->ddr.cs_config[3] = 0;
68 debug("cs0_bnds = 0x%08x\n", im->ddr.csbnds[0].csbnds);
69 debug("cs0_config = 0x%08x\n", im->ddr.cs_config[0]);
71 debug("DDR:bar=0x%08x\n", im->sysconf.ddrlaw[0].bar);
72 debug("DDR:ar=0x%08x\n", im->sysconf.ddrlaw[0].ar);
74 im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
75 im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;/* Was "2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT" */
76 im->ddr.sdram_cfg = SDRAM_CFG_SREN | SDRAM_CFG_SDRAM_TYPE_DDR1;
78 (0x0000 << SDRAM_MODE_ESD_SHIFT) | (0x0032 << SDRAM_MODE_SD_SHIFT);
79 im->ddr.sdram_interval =
80 (0x0410 << SDRAM_INTERVAL_REFINT_SHIFT) | (0x0100 <<
81 SDRAM_INTERVAL_BSTOPRE_SHIFT);
82 im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL;
86 im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
88 debug("DDR:timing_cfg_1=0x%08x\n", im->ddr.timing_cfg_1);
89 debug("DDR:timing_cfg_2=0x%08x\n", im->ddr.timing_cfg_2);
90 debug("DDR:sdram_mode=0x%08x\n", im->ddr.sdram_mode);
91 debug("DDR:sdram_interval=0x%08x\n", im->ddr.sdram_interval);
92 debug("DDR:sdram_cfg=0x%08x\n", im->ddr.sdram_cfg);
94 return CONFIG_SYS_DDR_SIZE;
100 * Initialize PCI Devices, report devices found
102 #ifndef CONFIG_PCI_PNP
103 static struct pci_config_table pci_mpc83xxmitx_config_table[] = {
111 pci_cfgfunc_config_device,
115 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER}
121 volatile static struct pci_controller hose[] = {
123 #ifndef CONFIG_PCI_PNP
124 config_table:pci_mpc83xxmitx_config_table,
128 #ifndef CONFIG_PCI_PNP
129 config_table:pci_mpc83xxmitx_config_table,
133 #endif /* CONFIG_PCI */
135 phys_size_t initdram(int board_type)
137 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
139 #ifdef CONFIG_DDR_ECC
140 volatile ddr83xx_t *ddr = &im->ddr;
143 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
146 /* DDR SDRAM - Main SODIMM */
147 im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
148 #ifdef CONFIG_SPD_EEPROM
151 msize = fixed_sdram();
154 #ifdef CONFIG_DDR_ECC
155 if (ddr->sdram_cfg & SDRAM_CFG_ECC_EN)
156 /* Unlike every other board, on the 83xx spd_sdram() returns
157 megabytes instead of just bytes. That's why we need to
158 multiple by 1MB when calling ddr_enable_ecc(). */
159 ddr_enable_ecc(msize * 1048576);
162 /* return total bus RAM size(bytes) */
163 return msize * 1024 * 1024;
168 #ifdef CONFIG_MPC8349ITX
169 puts("Board: Freescale MPC8349E-mITX\n");
171 puts("Board: Freescale MPC8349E-mITX-GP\n");
178 * Implement a work-around for a hardware problem with compact
181 * Program the UPM if compact flash is enabled.
183 int misc_init_f(void)
185 #ifdef CONFIG_VSC7385_ENET
186 volatile u32 *vsc7385_cpuctrl;
188 /* 0x1c0c0 is the VSC7385 CPU Control (CPUCTRL) Register. The power up
189 default of VSC7385 L1_IRQ and L2_IRQ requests are active high. That
190 means it is 0 when the IRQ is not active. This makes the wire-AND
191 logic always assert IRQ7 to CPU even if there is no request from the
192 switch. Since the compact flash and the switch share the same IRQ,
193 the Linux kernel will think that the compact flash is requesting irq
194 and get stuck when it tries to clear the IRQ. Thus we need to set
195 the L2_IRQ0 and L2_IRQ1 to active low.
197 The following code sets the L1_IRQ and L2_IRQ polarity to active low.
198 Without this code, compact flash will not work in Linux because
199 unlike U-Boot, Linux uses the IRQ, so this code is necessary if we
200 don't enable compact flash for U-Boot.
203 vsc7385_cpuctrl = (volatile u32 *)(CONFIG_SYS_VSC7385_BASE + 0x1c0c0);
204 *vsc7385_cpuctrl |= 0x0c;
207 #ifdef CONFIG_COMPACT_FLASH
208 /* UPM Table Configuration Code */
209 static uint UPMATable[] = {
210 0xcffffc00, 0x0fffff00, 0x0fafff00, 0x0fafff00,
211 0x0faffd00, 0x0faffc04, 0x0ffffc00, 0x3ffffc01,
212 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
213 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
214 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfff7fc00,
215 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
216 0xcffffc00, 0x0fffff00, 0x0ff3ff00, 0x0ff3ff00,
217 0x0ff3fe00, 0x0ffffc00, 0x3ffffc05, 0xfffffc00,
218 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
219 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
220 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
221 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
222 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
223 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
224 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
225 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01
227 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
229 set_lbc_br(3, CONFIG_SYS_BR3_PRELIM);
230 set_lbc_or(3, CONFIG_SYS_OR3_PRELIM);
232 /* Program the MAMR. RFEN=0, OP=00, UWPL=1, AM=000, DS=01, G0CL=000,
233 GPL4=0, RLF=0001, WLF=0001, TLF=0001, MAD=000000
235 immap->im_lbc.mamr = 0x08404440;
237 upmconfig(0, UPMATable, sizeof(UPMATable) / sizeof(UPMATable[0]));
239 puts("UPMA: Configured for compact flash\n");
246 * Miscellaneous late-boot configurations
248 * Make sure the EEPROM has the HRCW correctly programmed.
249 * Make sure the RTC is correctly programmed.
251 * The MPC8349E-mITX can be configured to load the HRCW from
252 * EEPROM instead of flash. This is controlled via jumpers
253 * LGPL0, 1, and 3. Normally, these jumpers are set to 000 (all
254 * jumpered), but if they're set to 001 or 010, then the HRCW is
255 * read from the "I2C EEPROM".
257 * This function makes sure that the I2C EEPROM is programmed
260 * If a VSC7385 microcode image is present, then upload it.
262 int misc_init_r(void)
266 #if defined(CONFIG_SYS_I2C)
267 unsigned int orig_bus = i2c_get_bus_num();
270 #ifdef CONFIG_SYS_I2C_RTC_ADDR
274 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR
275 static u8 eeprom_data[] = /* HRCW data */
277 0xAA, 0x55, 0xAA, /* Preamble */
278 0x7C, /* ACS=0, BYTE_EN=1111, CONT=1 */
279 0x02, 0x40, /* RCWL ADDR=0x0_0900 */
280 (CONFIG_SYS_HRCW_LOW >> 24) & 0xFF,
281 (CONFIG_SYS_HRCW_LOW >> 16) & 0xFF,
282 (CONFIG_SYS_HRCW_LOW >> 8) & 0xFF,
283 CONFIG_SYS_HRCW_LOW & 0xFF,
284 0x7C, /* ACS=0, BYTE_EN=1111, CONT=1 */
285 0x02, 0x41, /* RCWH ADDR=0x0_0904 */
286 (CONFIG_SYS_HRCW_HIGH >> 24) & 0xFF,
287 (CONFIG_SYS_HRCW_HIGH >> 16) & 0xFF,
288 (CONFIG_SYS_HRCW_HIGH >> 8) & 0xFF,
289 CONFIG_SYS_HRCW_HIGH & 0xFF
292 u8 data[sizeof(eeprom_data)];
295 printf("Board revision: ");
297 if (i2c_read(CONFIG_SYS_I2C_8574A_ADDR2, 0, 0, &i2c_data, sizeof(i2c_data)) == 0)
298 printf("%u.%u (PCF8475A)\n", (i2c_data & 0x02) >> 1, i2c_data & 0x01);
299 else if (i2c_read(CONFIG_SYS_I2C_8574_ADDR2, 0, 0, &i2c_data, sizeof(i2c_data)) == 0)
300 printf("%u.%u (PCF8475)\n", (i2c_data & 0x02) >> 1, i2c_data & 0x01);
306 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR
309 if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, data, sizeof(data)) == 0) {
310 if (memcmp(data, eeprom_data, sizeof(data)) != 0) {
312 (CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, eeprom_data,
313 sizeof(eeprom_data)) != 0) {
314 puts("Failure writing the HRCW to EEPROM via I2C.\n");
319 puts("Failure reading the HRCW from EEPROM via I2C.\n");
324 #ifdef CONFIG_SYS_I2C_RTC_ADDR
327 if (i2c_read(CONFIG_SYS_I2C_RTC_ADDR, 0, 1, ds1339_data, sizeof(ds1339_data))
330 /* Work-around for MPC8349E-mITX bug #13601.
331 If the RTC does not contain valid register values, the DS1339
332 Linux driver will not work.
335 /* Make sure status register bits 6-2 are zero */
336 ds1339_data[0x0f] &= ~0x7c;
338 /* Check for a valid day register value */
339 ds1339_data[0x03] &= ~0xf8;
340 if (ds1339_data[0x03] == 0) {
341 ds1339_data[0x03] = 1;
344 /* Check for a valid date register value */
345 ds1339_data[0x04] &= ~0xc0;
346 if ((ds1339_data[0x04] == 0) ||
347 ((ds1339_data[0x04] & 0x0f) > 9) ||
348 (ds1339_data[0x04] >= 0x32)) {
349 ds1339_data[0x04] = 1;
352 /* Check for a valid month register value */
353 ds1339_data[0x05] &= ~0x60;
355 if ((ds1339_data[0x05] == 0) ||
356 ((ds1339_data[0x05] & 0x0f) > 9) ||
357 ((ds1339_data[0x05] >= 0x13)
358 && (ds1339_data[0x05] <= 0x19))) {
359 ds1339_data[0x05] = 1;
362 /* Enable Oscillator and rate select */
363 ds1339_data[0x0e] = 0x1c;
365 /* Work-around for MPC8349E-mITX bug #13330.
366 Ensure that the RTC control register contains the value 0x1c.
367 This affects SATA performance.
371 (CONFIG_SYS_I2C_RTC_ADDR, 0, 1, ds1339_data,
372 sizeof(ds1339_data))) {
373 puts("Failure writing to the RTC via I2C.\n");
377 puts("Failure reading from the RTC via I2C.\n");
382 i2c_set_bus_num(orig_bus);
385 #ifdef CONFIG_VSC7385_IMAGE
386 if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE,
387 CONFIG_VSC7385_IMAGE_SIZE)) {
388 puts("Failure uploading VSC7385 microcode.\n");
396 #if defined(CONFIG_OF_BOARD_SETUP)
397 void ft_board_setup(void *blob, bd_t *bd)
399 ft_cpu_setup(blob, bd);
401 ft_pci_setup(blob, bd);