2 * Copyright (C) Freescale Semiconductor, Inc. 2006.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 #include <asm/mpc8349_pci.h>
33 #include <spd_sdram.h>
35 #if defined(CONFIG_OF_LIBFDT)
39 #ifndef CONFIG_SPD_EEPROM
40 /*************************************************************************
41 * fixed sdram init -- doesn't use serial presence detect.
42 ************************************************************************/
45 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
46 u32 ddr_size; /* The size of RAM, in bytes */
47 u32 ddr_size_log2 = 0;
49 for (ddr_size = CONFIG_SYS_DDR_SIZE * 0x100000; ddr_size > 1; ddr_size >>= 1) {
56 im->sysconf.ddrlaw[0].ar =
57 LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
58 im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
60 /* Only one CS0 for DDR */
61 im->ddr.csbnds[0].csbnds = 0x0000000f;
62 im->ddr.cs_config[0] = CONFIG_SYS_DDR_CONFIG;
64 debug("cs0_bnds = 0x%08x\n", im->ddr.csbnds[0].csbnds);
65 debug("cs0_config = 0x%08x\n", im->ddr.cs_config[0]);
67 debug("DDR:bar=0x%08x\n", im->sysconf.ddrlaw[0].bar);
68 debug("DDR:ar=0x%08x\n", im->sysconf.ddrlaw[0].ar);
70 im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
71 im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;/* Was "2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT" */
72 im->ddr.sdram_cfg = SDRAM_CFG_SREN | SDRAM_CFG_SDRAM_TYPE_DDR1;
74 (0x0000 << SDRAM_MODE_ESD_SHIFT) | (0x0032 << SDRAM_MODE_SD_SHIFT);
75 im->ddr.sdram_interval =
76 (0x0410 << SDRAM_INTERVAL_REFINT_SHIFT) | (0x0100 <<
77 SDRAM_INTERVAL_BSTOPRE_SHIFT);
78 im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL;
82 im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
84 debug("DDR:timing_cfg_1=0x%08x\n", im->ddr.timing_cfg_1);
85 debug("DDR:timing_cfg_2=0x%08x\n", im->ddr.timing_cfg_2);
86 debug("DDR:sdram_mode=0x%08x\n", im->ddr.sdram_mode);
87 debug("DDR:sdram_interval=0x%08x\n", im->ddr.sdram_interval);
88 debug("DDR:sdram_cfg=0x%08x\n", im->ddr.sdram_cfg);
90 return CONFIG_SYS_DDR_SIZE;
96 * Initialize PCI Devices, report devices found
98 #ifndef CONFIG_PCI_PNP
99 static struct pci_config_table pci_mpc83xxmitx_config_table[] = {
107 pci_cfgfunc_config_device,
111 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER}
117 volatile static struct pci_controller hose[] = {
119 #ifndef CONFIG_PCI_PNP
120 config_table:pci_mpc83xxmitx_config_table,
124 #ifndef CONFIG_PCI_PNP
125 config_table:pci_mpc83xxmitx_config_table,
129 #endif /* CONFIG_PCI */
131 phys_size_t initdram(int board_type)
133 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
135 #ifdef CONFIG_DDR_ECC
136 volatile ddr83xx_t *ddr = &im->ddr;
139 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
142 /* DDR SDRAM - Main SODIMM */
143 im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
144 #ifdef CONFIG_SPD_EEPROM
147 msize = fixed_sdram();
150 #ifdef CONFIG_DDR_ECC
151 if (ddr->sdram_cfg & SDRAM_CFG_ECC_EN)
152 /* Unlike every other board, on the 83xx spd_sdram() returns
153 megabytes instead of just bytes. That's why we need to
154 multiple by 1MB when calling ddr_enable_ecc(). */
155 ddr_enable_ecc(msize * 1048576);
158 /* return total bus RAM size(bytes) */
159 return msize * 1024 * 1024;
164 #ifdef CONFIG_MPC8349ITX
165 puts("Board: Freescale MPC8349E-mITX\n");
167 puts("Board: Freescale MPC8349E-mITX-GP\n");
174 * Implement a work-around for a hardware problem with compact
177 * Program the UPM if compact flash is enabled.
179 int misc_init_f(void)
181 #ifdef CONFIG_VSC7385_ENET
182 volatile u32 *vsc7385_cpuctrl;
184 /* 0x1c0c0 is the VSC7385 CPU Control (CPUCTRL) Register. The power up
185 default of VSC7385 L1_IRQ and L2_IRQ requests are active high. That
186 means it is 0 when the IRQ is not active. This makes the wire-AND
187 logic always assert IRQ7 to CPU even if there is no request from the
188 switch. Since the compact flash and the switch share the same IRQ,
189 the Linux kernel will think that the compact flash is requesting irq
190 and get stuck when it tries to clear the IRQ. Thus we need to set
191 the L2_IRQ0 and L2_IRQ1 to active low.
193 The following code sets the L1_IRQ and L2_IRQ polarity to active low.
194 Without this code, compact flash will not work in Linux because
195 unlike U-Boot, Linux uses the IRQ, so this code is necessary if we
196 don't enable compact flash for U-Boot.
199 vsc7385_cpuctrl = (volatile u32 *)(CONFIG_SYS_VSC7385_BASE + 0x1c0c0);
200 *vsc7385_cpuctrl |= 0x0c;
203 #ifdef CONFIG_COMPACT_FLASH
204 /* UPM Table Configuration Code */
205 static uint UPMATable[] = {
206 0xcffffc00, 0x0fffff00, 0x0fafff00, 0x0fafff00,
207 0x0faffd00, 0x0faffc04, 0x0ffffc00, 0x3ffffc01,
208 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
209 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
210 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfff7fc00,
211 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
212 0xcffffc00, 0x0fffff00, 0x0ff3ff00, 0x0ff3ff00,
213 0x0ff3fe00, 0x0ffffc00, 0x3ffffc05, 0xfffffc00,
214 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
215 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
216 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
217 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
218 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
219 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
220 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
221 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01
223 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
225 set_lbc_br(3, CONFIG_SYS_BR3_PRELIM);
226 set_lbc_or(3, CONFIG_SYS_OR3_PRELIM);
228 /* Program the MAMR. RFEN=0, OP=00, UWPL=1, AM=000, DS=01, G0CL=000,
229 GPL4=0, RLF=0001, WLF=0001, TLF=0001, MAD=000000
231 immap->im_lbc.mamr = 0x08404440;
233 upmconfig(0, UPMATable, sizeof(UPMATable) / sizeof(UPMATable[0]));
235 puts("UPMA: Configured for compact flash\n");
242 * Miscellaneous late-boot configurations
244 * Make sure the EEPROM has the HRCW correctly programmed.
245 * Make sure the RTC is correctly programmed.
247 * The MPC8349E-mITX can be configured to load the HRCW from
248 * EEPROM instead of flash. This is controlled via jumpers
249 * LGPL0, 1, and 3. Normally, these jumpers are set to 000 (all
250 * jumpered), but if they're set to 001 or 010, then the HRCW is
251 * read from the "I2C EEPROM".
253 * This function makes sure that the I2C EEPROM is programmed
256 * If a VSC7385 microcode image is present, then upload it.
258 int misc_init_r(void)
262 #ifdef CONFIG_HARD_I2C
264 unsigned int orig_bus = i2c_get_bus_num();
267 #ifdef CONFIG_SYS_I2C_RTC_ADDR
271 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR
272 static u8 eeprom_data[] = /* HRCW data */
274 0xAA, 0x55, 0xAA, /* Preamble */
275 0x7C, /* ACS=0, BYTE_EN=1111, CONT=1 */
276 0x02, 0x40, /* RCWL ADDR=0x0_0900 */
277 (CONFIG_SYS_HRCW_LOW >> 24) & 0xFF,
278 (CONFIG_SYS_HRCW_LOW >> 16) & 0xFF,
279 (CONFIG_SYS_HRCW_LOW >> 8) & 0xFF,
280 CONFIG_SYS_HRCW_LOW & 0xFF,
281 0x7C, /* ACS=0, BYTE_EN=1111, CONT=1 */
282 0x02, 0x41, /* RCWH ADDR=0x0_0904 */
283 (CONFIG_SYS_HRCW_HIGH >> 24) & 0xFF,
284 (CONFIG_SYS_HRCW_HIGH >> 16) & 0xFF,
285 (CONFIG_SYS_HRCW_HIGH >> 8) & 0xFF,
286 CONFIG_SYS_HRCW_HIGH & 0xFF
289 u8 data[sizeof(eeprom_data)];
292 printf("Board revision: ");
294 if (i2c_read(CONFIG_SYS_I2C_8574A_ADDR2, 0, 0, &i2c_data, sizeof(i2c_data)) == 0)
295 printf("%u.%u (PCF8475A)\n", (i2c_data & 0x02) >> 1, i2c_data & 0x01);
296 else if (i2c_read(CONFIG_SYS_I2C_8574_ADDR2, 0, 0, &i2c_data, sizeof(i2c_data)) == 0)
297 printf("%u.%u (PCF8475)\n", (i2c_data & 0x02) >> 1, i2c_data & 0x01);
303 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR
306 if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, data, sizeof(data)) == 0) {
307 if (memcmp(data, eeprom_data, sizeof(data)) != 0) {
309 (CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, eeprom_data,
310 sizeof(eeprom_data)) != 0) {
311 puts("Failure writing the HRCW to EEPROM via I2C.\n");
316 puts("Failure reading the HRCW from EEPROM via I2C.\n");
321 #ifdef CONFIG_SYS_I2C_RTC_ADDR
324 if (i2c_read(CONFIG_SYS_I2C_RTC_ADDR, 0, 1, ds1339_data, sizeof(ds1339_data))
327 /* Work-around for MPC8349E-mITX bug #13601.
328 If the RTC does not contain valid register values, the DS1339
329 Linux driver will not work.
332 /* Make sure status register bits 6-2 are zero */
333 ds1339_data[0x0f] &= ~0x7c;
335 /* Check for a valid day register value */
336 ds1339_data[0x03] &= ~0xf8;
337 if (ds1339_data[0x03] == 0) {
338 ds1339_data[0x03] = 1;
341 /* Check for a valid date register value */
342 ds1339_data[0x04] &= ~0xc0;
343 if ((ds1339_data[0x04] == 0) ||
344 ((ds1339_data[0x04] & 0x0f) > 9) ||
345 (ds1339_data[0x04] >= 0x32)) {
346 ds1339_data[0x04] = 1;
349 /* Check for a valid month register value */
350 ds1339_data[0x05] &= ~0x60;
352 if ((ds1339_data[0x05] == 0) ||
353 ((ds1339_data[0x05] & 0x0f) > 9) ||
354 ((ds1339_data[0x05] >= 0x13)
355 && (ds1339_data[0x05] <= 0x19))) {
356 ds1339_data[0x05] = 1;
359 /* Enable Oscillator and rate select */
360 ds1339_data[0x0e] = 0x1c;
362 /* Work-around for MPC8349E-mITX bug #13330.
363 Ensure that the RTC control register contains the value 0x1c.
364 This affects SATA performance.
368 (CONFIG_SYS_I2C_RTC_ADDR, 0, 1, ds1339_data,
369 sizeof(ds1339_data))) {
370 puts("Failure writing to the RTC via I2C.\n");
374 puts("Failure reading from the RTC via I2C.\n");
379 i2c_set_bus_num(orig_bus);
382 #ifdef CONFIG_VSC7385_IMAGE
383 if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE,
384 CONFIG_VSC7385_IMAGE_SIZE)) {
385 puts("Failure uploading VSC7385 microcode.\n");
393 #if defined(CONFIG_OF_BOARD_SETUP)
394 void ft_board_setup(void *blob, bd_t *bd)
396 ft_cpu_setup(blob, bd);
398 ft_pci_setup(blob, bd);