2 * Copyright (C) 2006,2010 Freescale Semiconductor, Inc.
3 * Dave Liu <daveliu@freescale.com>
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
19 #if defined(CONFIG_PCI)
22 #include <spd_sdram.h>
25 #include <asm/fsl_enet.h>
26 #if defined(CONFIG_OF_LIBFDT)
30 #include <fdt_support.h>
31 #if defined(CONFIG_PQ_MDS_PIB)
32 #include "../common/pq-mds-pib.h"
34 #include "../../../drivers/qe/uec.h"
36 const qe_iop_conf_t qe_iop_conf_tab[] = {
38 {0, 3, 1, 0, 1}, /* TxD0 */
39 {0, 4, 1, 0, 1}, /* TxD1 */
40 {0, 5, 1, 0, 1}, /* TxD2 */
41 {0, 6, 1, 0, 1}, /* TxD3 */
42 {1, 6, 1, 0, 3}, /* TxD4 */
43 {1, 7, 1, 0, 1}, /* TxD5 */
44 {1, 9, 1, 0, 2}, /* TxD6 */
45 {1, 10, 1, 0, 2}, /* TxD7 */
46 {0, 9, 2, 0, 1}, /* RxD0 */
47 {0, 10, 2, 0, 1}, /* RxD1 */
48 {0, 11, 2, 0, 1}, /* RxD2 */
49 {0, 12, 2, 0, 1}, /* RxD3 */
50 {0, 13, 2, 0, 1}, /* RxD4 */
51 {1, 1, 2, 0, 2}, /* RxD5 */
52 {1, 0, 2, 0, 2}, /* RxD6 */
53 {1, 4, 2, 0, 2}, /* RxD7 */
54 {0, 7, 1, 0, 1}, /* TX_EN */
55 {0, 8, 1, 0, 1}, /* TX_ER */
56 {0, 15, 2, 0, 1}, /* RX_DV */
57 {0, 16, 2, 0, 1}, /* RX_ER */
58 {0, 0, 2, 0, 1}, /* RX_CLK */
59 {2, 9, 1, 0, 3}, /* GTX_CLK - CLK10 */
60 {2, 8, 2, 0, 1}, /* GTX125 - CLK9 */
62 {0, 17, 1, 0, 1}, /* TxD0 */
63 {0, 18, 1, 0, 1}, /* TxD1 */
64 {0, 19, 1, 0, 1}, /* TxD2 */
65 {0, 20, 1, 0, 1}, /* TxD3 */
66 {1, 2, 1, 0, 1}, /* TxD4 */
67 {1, 3, 1, 0, 2}, /* TxD5 */
68 {1, 5, 1, 0, 3}, /* TxD6 */
69 {1, 8, 1, 0, 3}, /* TxD7 */
70 {0, 23, 2, 0, 1}, /* RxD0 */
71 {0, 24, 2, 0, 1}, /* RxD1 */
72 {0, 25, 2, 0, 1}, /* RxD2 */
73 {0, 26, 2, 0, 1}, /* RxD3 */
74 {0, 27, 2, 0, 1}, /* RxD4 */
75 {1, 12, 2, 0, 2}, /* RxD5 */
76 {1, 13, 2, 0, 3}, /* RxD6 */
77 {1, 11, 2, 0, 2}, /* RxD7 */
78 {0, 21, 1, 0, 1}, /* TX_EN */
79 {0, 22, 1, 0, 1}, /* TX_ER */
80 {0, 29, 2, 0, 1}, /* RX_DV */
81 {0, 30, 2, 0, 1}, /* RX_ER */
82 {0, 31, 2, 0, 1}, /* RX_CLK */
83 {2, 2, 1, 0, 2}, /* GTX_CLK = CLK10 */
84 {2, 3, 2, 0, 1}, /* GTX125 - CLK4 */
86 {0, 1, 3, 0, 2}, /* MDIO */
87 {0, 2, 1, 0, 1}, /* MDC */
89 {5, 0, 1, 0, 2}, /* UART2_SOUT */
90 {5, 1, 2, 0, 3}, /* UART2_CTS */
91 {5, 2, 1, 0, 1}, /* UART2_RTS */
92 {5, 3, 2, 0, 2}, /* UART2_SIN */
94 {0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */
97 /* Handle "mpc8360ea rev.2.1 erratum 2: RGMII Timing"? */
98 static int board_handle_erratum2(void)
100 const immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
102 return REVID_MAJOR(immr->sysconf.spridr) == 2 &&
103 REVID_MINOR(immr->sysconf.spridr) == 1;
106 int board_early_init_f(void)
108 const immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
109 u8 *bcsr = (u8 *)CONFIG_SYS_BCSR;
111 /* Enable flash write */
114 /* Disable G1TXCLK, G2TXCLK h/w buffers (rev.2.x h/w bug workaround) */
115 if (REVID_MAJOR(immr->sysconf.spridr) == 2)
118 /* Enable second UART */
121 if (board_handle_erratum2()) {
122 void *immap = (immap_t *)(CONFIG_SYS_IMMR + 0x14a8);
125 * IMMR + 0x14A8[4:5] = 11 (clk delay for UCC 2)
126 * IMMR + 0x14A8[18:19] = 11 (clk delay for UCC 1)
128 setbits_be32(immap, 0x0c003000);
131 * IMMR + 0x14AC[20:27] = 10101010
132 * (data delay for both UCC's)
134 clrsetbits_be32(immap + 4, 0xff0, 0xaa0);
139 int board_early_init_r(void)
141 #ifdef CONFIG_PQ_MDS_PIB
147 #ifdef CONFIG_UEC_ETH
148 static uec_info_t uec_info[] = {
149 #ifdef CONFIG_UEC_ETH1
152 #ifdef CONFIG_UEC_ETH2
157 int board_eth_init(bd_t *bd)
159 if (board_handle_erratum2()) {
162 for (i = 0; i < ARRAY_SIZE(uec_info); i++)
163 uec_info[i].enet_interface_type = RGMII_RXID;
164 uec_info[i].speed = 1000;
166 return uec_eth_init(bd, uec_info, ARRAY_SIZE(uec_info));
168 #endif /* CONFIG_UEC_ETH */
170 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
171 extern void ddr_enable_ecc(unsigned int dram_size);
173 int fixed_sdram(void);
174 static int sdram_init(unsigned int base);
176 phys_size_t initdram(int board_type)
178 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
182 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
185 /* DDR SDRAM - Main SODIMM */
186 im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
187 #if defined(CONFIG_SPD_EEPROM)
190 msize = fixed_sdram();
193 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
195 * Initialize DDR ECC byte
197 ddr_enable_ecc(msize * 1024 * 1024);
200 * Initialize SDRAM if it is on local bus.
202 lbc_sdram_size = sdram_init(msize * 1024 * 1024);
204 msize = lbc_sdram_size;
206 /* return total bus SDRAM size(bytes) -- DDR */
207 return (msize * 1024 * 1024);
210 #if !defined(CONFIG_SPD_EEPROM)
211 /*************************************************************************
212 * fixed sdram init -- doesn't use serial presence detect.
213 ************************************************************************/
214 int fixed_sdram(void)
216 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
221 msize = CONFIG_SYS_DDR_SIZE;
222 for (ddr_size = msize << 20, ddr_size_log2 = 0;
223 (ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) {
228 im->sysconf.ddrlaw[0].ar =
229 LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
230 #if (CONFIG_SYS_DDR_SIZE != 256)
231 #warning Currenly any ddr size other than 256 is not supported
234 im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
235 im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
236 im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
237 im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
238 im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
239 im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
240 im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
241 im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
242 im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
243 im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
244 im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
245 im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
247 im->ddr.csbnds[0].csbnds = 0x00000007;
248 im->ddr.csbnds[1].csbnds = 0x0008000f;
250 im->ddr.cs_config[0] = CONFIG_SYS_DDR_CONFIG;
251 im->ddr.cs_config[1] = CONFIG_SYS_DDR_CONFIG;
253 im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
254 im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
255 im->ddr.sdram_cfg = CONFIG_SYS_DDR_CONTROL;
257 im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
258 im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
261 im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
265 #endif /*!CONFIG_SYS_SPD_EEPROM */
269 puts("Board: Freescale MPC8360EMDS\n");
274 * if MPC8360EMDS is soldered with SDRAM
276 #ifdef CONFIG_SYS_LB_SDRAM
278 * Initialize SDRAM memory on the Local Bus.
281 static int sdram_init(unsigned int base)
283 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
284 fsl_lbc_t *lbc = LBC_BASE_ADDR;
285 const int sdram_size = CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024;
286 int rem = base % sdram_size;
289 /* window base address should be aligned to the window size */
291 base = base - rem + sdram_size;
293 sdram_addr = (uint *)base;
295 * Setup SDRAM Base and Option Registers
297 set_lbc_br(2, base | CONFIG_SYS_BR2);
298 set_lbc_or(2, CONFIG_SYS_OR2);
299 immap->sysconf.lblaw[2].bar = base;
300 immap->sysconf.lblaw[2].ar = CONFIG_SYS_LBLAWAR2;
302 /*setup mtrpt, lsrt and lbcr for LB bus */
303 lbc->lbcr = CONFIG_SYS_LBC_LBCR;
304 lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
305 lbc->lsrt = CONFIG_SYS_LBC_LSRT;
309 * Configure the SDRAM controller Machine Mode Register.
311 lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* Normal Operation */
312 lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1; /* Precharge All Banks */
318 * We need do 8 times auto refresh operation.
320 lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2;
322 *sdram_addr = 0xff; /* 1 times */
324 *sdram_addr = 0xff; /* 2 times */
326 *sdram_addr = 0xff; /* 3 times */
328 *sdram_addr = 0xff; /* 4 times */
330 *sdram_addr = 0xff; /* 5 times */
332 *sdram_addr = 0xff; /* 6 times */
334 *sdram_addr = 0xff; /* 7 times */
336 *sdram_addr = 0xff; /* 8 times */
339 /* Mode register write operation */
340 lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4;
342 *(sdram_addr + 0xcc) = 0xff;
345 /* Normal operation */
346 lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5 | 0x40000000;
352 * In non-aligned case we don't [normally] use that memory because
357 return CONFIG_SYS_LBC_SDRAM_SIZE;
360 static int sdram_init(unsigned int base) { return 0; }
363 #if defined(CONFIG_OF_BOARD_SETUP)
364 static void ft_board_fixup_qe_usb(void *blob, bd_t *bd)
366 if (!hwconfig_subarg_cmp("qe_usb", "mode", "peripheral"))
369 do_fixup_by_compat(blob, "fsl,mpc8323-qe-usb", "mode",
370 "peripheral", sizeof("peripheral"), 1);
373 void ft_board_setup(void *blob, bd_t *bd)
375 ft_cpu_setup(blob, bd);
377 ft_pci_setup(blob, bd);
379 ft_board_fixup_qe_usb(blob, bd);
381 * mpc8360ea pb mds errata 2: RGMII timing
382 * if on mpc8360ea rev. 2.1,
383 * change both ucc phy-connection-types from rgmii-id to rgmii-rxid
385 if (board_handle_erratum2()) {
390 nodeoffset = fdt_path_offset(blob, "/aliases");
391 if (nodeoffset >= 0) {
392 #if defined(CONFIG_HAS_ETH0)
393 /* fixup UCC 1 if using rgmii-id mode */
394 prop = fdt_getprop(blob, nodeoffset, "ethernet0", NULL);
396 path = fdt_path_offset(blob, prop);
397 prop = fdt_getprop(blob, path,
398 "phy-connection-type", 0);
399 if (prop && (strcmp(prop, "rgmii-id") == 0))
400 fdt_fixup_phy_connection(blob, path,
404 #if defined(CONFIG_HAS_ETH1)
405 /* fixup UCC 2 if using rgmii-id mode */
406 prop = fdt_getprop(blob, nodeoffset, "ethernet1", NULL);
408 path = fdt_path_offset(blob, prop);
409 prop = fdt_getprop(blob, path,
410 "phy-connection-type", 0);
411 if (prop && (strcmp(prop, "rgmii-id") == 0))
412 fdt_fixup_phy_connection(blob, path,