2 * Copyright (C) 2006,2010-2011 Freescale Semiconductor, Inc.
3 * Dave Liu <daveliu@freescale.com>
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
20 #if defined(CONFIG_PCI)
23 #include <spd_sdram.h>
26 #include <asm/fsl_enet.h>
28 #if defined(CONFIG_OF_LIBFDT)
32 #include <fdt_support.h>
33 #if defined(CONFIG_PQ_MDS_PIB)
34 #include "../common/pq-mds-pib.h"
36 #include "../../../drivers/qe/uec.h"
38 const qe_iop_conf_t qe_iop_conf_tab[] = {
40 {0, 3, 1, 0, 1}, /* TxD0 */
41 {0, 4, 1, 0, 1}, /* TxD1 */
42 {0, 5, 1, 0, 1}, /* TxD2 */
43 {0, 6, 1, 0, 1}, /* TxD3 */
44 {1, 6, 1, 0, 3}, /* TxD4 */
45 {1, 7, 1, 0, 1}, /* TxD5 */
46 {1, 9, 1, 0, 2}, /* TxD6 */
47 {1, 10, 1, 0, 2}, /* TxD7 */
48 {0, 9, 2, 0, 1}, /* RxD0 */
49 {0, 10, 2, 0, 1}, /* RxD1 */
50 {0, 11, 2, 0, 1}, /* RxD2 */
51 {0, 12, 2, 0, 1}, /* RxD3 */
52 {0, 13, 2, 0, 1}, /* RxD4 */
53 {1, 1, 2, 0, 2}, /* RxD5 */
54 {1, 0, 2, 0, 2}, /* RxD6 */
55 {1, 4, 2, 0, 2}, /* RxD7 */
56 {0, 7, 1, 0, 1}, /* TX_EN */
57 {0, 8, 1, 0, 1}, /* TX_ER */
58 {0, 15, 2, 0, 1}, /* RX_DV */
59 {0, 16, 2, 0, 1}, /* RX_ER */
60 {0, 0, 2, 0, 1}, /* RX_CLK */
61 {2, 9, 1, 0, 3}, /* GTX_CLK - CLK10 */
62 {2, 8, 2, 0, 1}, /* GTX125 - CLK9 */
64 {0, 17, 1, 0, 1}, /* TxD0 */
65 {0, 18, 1, 0, 1}, /* TxD1 */
66 {0, 19, 1, 0, 1}, /* TxD2 */
67 {0, 20, 1, 0, 1}, /* TxD3 */
68 {1, 2, 1, 0, 1}, /* TxD4 */
69 {1, 3, 1, 0, 2}, /* TxD5 */
70 {1, 5, 1, 0, 3}, /* TxD6 */
71 {1, 8, 1, 0, 3}, /* TxD7 */
72 {0, 23, 2, 0, 1}, /* RxD0 */
73 {0, 24, 2, 0, 1}, /* RxD1 */
74 {0, 25, 2, 0, 1}, /* RxD2 */
75 {0, 26, 2, 0, 1}, /* RxD3 */
76 {0, 27, 2, 0, 1}, /* RxD4 */
77 {1, 12, 2, 0, 2}, /* RxD5 */
78 {1, 13, 2, 0, 3}, /* RxD6 */
79 {1, 11, 2, 0, 2}, /* RxD7 */
80 {0, 21, 1, 0, 1}, /* TX_EN */
81 {0, 22, 1, 0, 1}, /* TX_ER */
82 {0, 29, 2, 0, 1}, /* RX_DV */
83 {0, 30, 2, 0, 1}, /* RX_ER */
84 {0, 31, 2, 0, 1}, /* RX_CLK */
85 {2, 2, 1, 0, 2}, /* GTX_CLK = CLK10 */
86 {2, 3, 2, 0, 1}, /* GTX125 - CLK4 */
88 {0, 1, 3, 0, 2}, /* MDIO */
89 {0, 2, 1, 0, 1}, /* MDC */
91 {5, 0, 1, 0, 2}, /* UART2_SOUT */
92 {5, 1, 2, 0, 3}, /* UART2_CTS */
93 {5, 2, 1, 0, 1}, /* UART2_RTS */
94 {5, 3, 2, 0, 2}, /* UART2_SIN */
96 {0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */
99 /* Handle "mpc8360ea rev.2.1 erratum 2: RGMII Timing"? */
100 static int board_handle_erratum2(void)
102 const immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
104 return REVID_MAJOR(immr->sysconf.spridr) == 2 &&
105 REVID_MINOR(immr->sysconf.spridr) == 1;
108 int board_early_init_f(void)
110 const immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
111 u8 *bcsr = (u8 *)CONFIG_SYS_BCSR;
113 /* Enable flash write */
116 /* Disable G1TXCLK, G2TXCLK h/w buffers (rev.2.x h/w bug workaround) */
117 if (REVID_MAJOR(immr->sysconf.spridr) == 2)
120 /* Enable second UART */
123 if (board_handle_erratum2()) {
124 void *immap = (immap_t *)(CONFIG_SYS_IMMR + 0x14a8);
127 * IMMR + 0x14A8[4:5] = 11 (clk delay for UCC 2)
128 * IMMR + 0x14A8[18:19] = 11 (clk delay for UCC 1)
130 setbits_be32(immap, 0x0c003000);
133 * IMMR + 0x14AC[20:27] = 10101010
134 * (data delay for both UCC's)
136 clrsetbits_be32(immap + 4, 0xff0, 0xaa0);
141 int board_early_init_r(void)
144 #ifdef CONFIG_PQ_MDS_PIB
148 * BAT6 is used for SDRAM when DDR size is 512MB or larger than 256MB
149 * So re-setup PCI MEM space used BAT5 after relocated to DDR
151 gd = (gd_t *)(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
152 if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) {
153 write_bat(DBAT5, CONFIG_SYS_DBAT6U, CONFIG_SYS_DBAT6L);
154 write_bat(IBAT5, CONFIG_SYS_IBAT6U, CONFIG_SYS_IBAT6L);
160 #ifdef CONFIG_UEC_ETH
161 static uec_info_t uec_info[] = {
162 #ifdef CONFIG_UEC_ETH1
165 #ifdef CONFIG_UEC_ETH2
170 int board_eth_init(bd_t *bd)
172 if (board_handle_erratum2()) {
175 for (i = 0; i < ARRAY_SIZE(uec_info); i++) {
176 uec_info[i].enet_interface_type =
177 PHY_INTERFACE_MODE_RGMII_RXID;
178 uec_info[i].speed = SPEED_1000;
181 return uec_eth_init(bd, uec_info, ARRAY_SIZE(uec_info));
183 #endif /* CONFIG_UEC_ETH */
185 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
186 extern void ddr_enable_ecc(unsigned int dram_size);
188 int fixed_sdram(void);
189 static int sdram_init(unsigned int base);
191 phys_size_t initdram(int board_type)
193 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
197 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
200 /* DDR SDRAM - Main SODIMM */
201 im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
202 #if defined(CONFIG_SPD_EEPROM)
205 msize = fixed_sdram();
208 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
210 * Initialize DDR ECC byte
212 ddr_enable_ecc(msize * 1024 * 1024);
215 * Initialize SDRAM if it is on local bus.
217 lbc_sdram_size = sdram_init(msize * 1024 * 1024);
219 msize = lbc_sdram_size;
221 /* return total bus SDRAM size(bytes) -- DDR */
222 return (msize * 1024 * 1024);
225 #if !defined(CONFIG_SPD_EEPROM)
226 /*************************************************************************
227 * fixed sdram init -- doesn't use serial presence detect.
228 ************************************************************************/
229 int fixed_sdram(void)
231 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
232 u32 msize = CONFIG_SYS_DDR_SIZE;
233 u32 ddr_size = msize << 20;
234 u32 ddr_size_log2 = __ilog2(ddr_size);
235 u32 half_ddr_size = ddr_size >> 1;
237 im->sysconf.ddrlaw[0].bar =
238 CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
239 im->sysconf.ddrlaw[0].ar =
240 LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
241 #if (CONFIG_SYS_DDR_SIZE != 256)
242 #warning Currenly any ddr size other than 256 is not supported
245 im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
246 im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
247 im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
248 im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
249 im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
250 im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
251 im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
252 im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
253 im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
254 im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
255 im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
256 im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
259 #if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0)
260 #warning Chip select bounds is only configurable in 16MB increments
262 im->ddr.csbnds[0].csbnds =
263 ((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
264 (((CONFIG_SYS_DDR_SDRAM_BASE + half_ddr_size - 1) >>
265 CSBNDS_EA_SHIFT) & CSBNDS_EA);
266 im->ddr.csbnds[1].csbnds =
267 (((CONFIG_SYS_DDR_SDRAM_BASE + half_ddr_size) >>
268 CSBNDS_SA_SHIFT) & CSBNDS_SA) |
269 (((CONFIG_SYS_DDR_SDRAM_BASE + ddr_size - 1) >>
270 CSBNDS_EA_SHIFT) & CSBNDS_EA);
272 im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
273 im->ddr.cs_config[1] = CONFIG_SYS_DDR_CS1_CONFIG;
275 im->ddr.cs_config[2] = 0;
276 im->ddr.cs_config[3] = 0;
278 im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
279 im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
280 im->ddr.sdram_cfg = CONFIG_SYS_DDR_CONTROL;
282 im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
283 im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
286 im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
290 #endif /*!CONFIG_SYS_SPD_EEPROM */
294 puts("Board: Freescale MPC8360EMDS\n");
299 * if MPC8360EMDS is soldered with SDRAM
301 #ifdef CONFIG_SYS_LB_SDRAM
303 * Initialize SDRAM memory on the Local Bus.
306 static int sdram_init(unsigned int base)
308 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
309 fsl_lbc_t *lbc = LBC_BASE_ADDR;
310 const int sdram_size = CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024;
311 int rem = base % sdram_size;
314 /* window base address should be aligned to the window size */
316 base = base - rem + sdram_size;
319 * Setup BAT6 for SDRAM when DDR size is 512MB or larger than 256MB
320 * After relocated to DDR, reuse BAT5 for PCI MEM space
322 if (base > CONFIG_MAX_MEM_MAPPED) {
323 unsigned long batl = base | BATL_PP_10 | BATL_MEMCOHERENCE;
324 unsigned long batu = base | BATU_BL_64M | BATU_VS | BATU_VP;
326 /* Setup the BAT6 for SDRAM */
327 write_bat(DBAT6, batu, batl);
328 write_bat(IBAT6, batu, batl);
331 sdram_addr = (uint *)base;
333 * Setup SDRAM Base and Option Registers
335 set_lbc_br(2, base | CONFIG_SYS_BR2);
336 set_lbc_or(2, CONFIG_SYS_OR2);
337 immap->sysconf.lblaw[2].bar = base;
338 immap->sysconf.lblaw[2].ar = CONFIG_SYS_LBLAWAR2;
340 /*setup mtrpt, lsrt and lbcr for LB bus */
341 lbc->lbcr = CONFIG_SYS_LBC_LBCR;
342 lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
343 lbc->lsrt = CONFIG_SYS_LBC_LSRT;
347 * Configure the SDRAM controller Machine Mode Register.
349 lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* Normal Operation */
350 lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1; /* Precharge All Banks */
356 * We need do 8 times auto refresh operation.
358 lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2;
360 *sdram_addr = 0xff; /* 1 times */
362 *sdram_addr = 0xff; /* 2 times */
364 *sdram_addr = 0xff; /* 3 times */
366 *sdram_addr = 0xff; /* 4 times */
368 *sdram_addr = 0xff; /* 5 times */
370 *sdram_addr = 0xff; /* 6 times */
372 *sdram_addr = 0xff; /* 7 times */
374 *sdram_addr = 0xff; /* 8 times */
377 /* Mode register write operation */
378 lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4;
380 *(sdram_addr + 0xcc) = 0xff;
383 /* Normal operation */
384 lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5 | 0x40000000;
390 * In non-aligned case we don't [normally] use that memory because
395 return CONFIG_SYS_LBC_SDRAM_SIZE;
398 static int sdram_init(unsigned int base) { return 0; }
401 #if defined(CONFIG_OF_BOARD_SETUP)
402 static void ft_board_fixup_qe_usb(void *blob, bd_t *bd)
404 if (!hwconfig_subarg_cmp("qe_usb", "mode", "peripheral"))
407 do_fixup_by_compat(blob, "fsl,mpc8323-qe-usb", "mode",
408 "peripheral", sizeof("peripheral"), 1);
411 void ft_board_setup(void *blob, bd_t *bd)
413 ft_cpu_setup(blob, bd);
415 ft_pci_setup(blob, bd);
417 ft_board_fixup_qe_usb(blob, bd);
419 * mpc8360ea pb mds errata 2: RGMII timing
420 * if on mpc8360ea rev. 2.1,
421 * change both ucc phy-connection-types from rgmii-id to rgmii-rxid
423 if (board_handle_erratum2()) {
428 nodeoffset = fdt_path_offset(blob, "/aliases");
429 if (nodeoffset >= 0) {
430 #if defined(CONFIG_HAS_ETH0)
431 /* fixup UCC 1 if using rgmii-id mode */
432 prop = fdt_getprop(blob, nodeoffset, "ethernet0", NULL);
434 path = fdt_path_offset(blob, prop);
435 prop = fdt_getprop(blob, path,
436 "phy-connection-type", 0);
437 if (prop && (strcmp(prop, "rgmii-id") == 0))
438 fdt_fixup_phy_connection(blob, path,
439 PHY_INTERFACE_MODE_RGMII_RXID);
442 #if defined(CONFIG_HAS_ETH1)
443 /* fixup UCC 2 if using rgmii-id mode */
444 prop = fdt_getprop(blob, nodeoffset, "ethernet1", NULL);
446 path = fdt_path_offset(blob, prop);
447 prop = fdt_getprop(blob, path,
448 "phy-connection-type", 0);
449 if (prop && (strcmp(prop, "rgmii-id") == 0))
450 fdt_fixup_phy_connection(blob, path,
451 PHY_INTERFACE_MODE_RGMII_RXID);