2 * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
8 * PCI Configuration space access support for MPC83xx PCI Bridge
17 #include <asm/fsl_i2c.h>
18 #include "../common/pq-mds-pib.h"
20 DECLARE_GLOBAL_DATA_PTR;
22 static struct pci_region pci1_regions[] = {
24 bus_start: CONFIG_SYS_PCI1_MEM_BASE,
25 phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
26 size: CONFIG_SYS_PCI1_MEM_SIZE,
27 flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
30 bus_start: CONFIG_SYS_PCI1_IO_BASE,
31 phys_start: CONFIG_SYS_PCI1_IO_PHYS,
32 size: CONFIG_SYS_PCI1_IO_SIZE,
36 bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
37 phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
38 size: CONFIG_SYS_PCI1_MMIO_SIZE,
43 #ifdef CONFIG_MPC83XX_PCI2
44 static struct pci_region pci2_regions[] = {
46 bus_start: CONFIG_SYS_PCI2_MEM_BASE,
47 phys_start: CONFIG_SYS_PCI2_MEM_PHYS,
48 size: CONFIG_SYS_PCI2_MEM_SIZE,
49 flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
52 bus_start: CONFIG_SYS_PCI2_IO_BASE,
53 phys_start: CONFIG_SYS_PCI2_IO_PHYS,
54 size: CONFIG_SYS_PCI2_IO_SIZE,
58 bus_start: CONFIG_SYS_PCI2_MMIO_BASE,
59 phys_start: CONFIG_SYS_PCI2_MMIO_PHYS,
60 size: CONFIG_SYS_PCI2_MMIO_SIZE,
66 void pci_init_board(void)
67 #ifdef CONFIG_PCISLAVE
69 volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
70 volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
71 volatile pcictrl83xx_t *pci_ctrl = &immr->pci_ctrl[0];
72 struct pci_region *reg[] = { pci1_regions };
74 /* Configure PCI Local Access Windows */
75 pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
76 pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_512M;
78 pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
79 pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_1M;
81 mpc83xx_pci_init(1, reg);
84 * Configure PCI Inbound Translation Windows
86 pci_ctrl[0].pitar0 = 0x0;
87 pci_ctrl[0].pibar0 = 0x0;
88 pci_ctrl[0].piwar0 = PIWAR_EN | PIWAR_RTT_SNOOP |
89 PIWAR_WTT_SNOOP | PIWAR_IWS_4K;
91 pci_ctrl[0].pitar1 = 0x0;
92 pci_ctrl[0].pibar1 = 0x0;
93 pci_ctrl[0].piebar1 = 0x0;
94 pci_ctrl[0].piwar1 &= ~PIWAR_EN;
96 pci_ctrl[0].pitar2 = 0x0;
97 pci_ctrl[0].pibar2 = 0x0;
98 pci_ctrl[0].piebar2 = 0x0;
99 pci_ctrl[0].piwar2 &= ~PIWAR_EN;
101 /* Unlock the configuration bit */
102 mpc83xx_pcislave_unlock(0);
103 printf("PCI: Agent mode enabled\n");
107 volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
108 volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
109 volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
110 #ifndef CONFIG_MPC83XX_PCI2
111 struct pci_region *reg[] = { pci1_regions };
113 struct pci_region *reg[] = { pci1_regions, pci2_regions };
116 /* initialize the PCA9555PW IO expander on the PIB board */
119 #if defined(CONFIG_PCI_66M)
120 clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2;
121 printf("PCI clock is 66MHz\n");
122 #elif defined(CONFIG_PCI_33M)
123 clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2 |
124 OCCR_PCICD0 | OCCR_PCICD1 | OCCR_PCICD2 | OCCR_PCICR;
125 printf("PCI clock is 33MHz\n");
127 clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2;
128 printf("PCI clock is 66MHz\n");
132 /* Configure PCI Local Access Windows */
133 pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
134 pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_512M;
136 pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
137 pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_1M;
141 #ifndef CONFIG_MPC83XX_PCI2
142 mpc83xx_pci_init(1, reg);
144 mpc83xx_pci_init(2, reg);
147 #endif /* CONFIG_PCISLAVE */