2 * Copyright (C) 2007,2010 Freescale Semiconductor, Inc.
3 * Dave Liu <daveliu@freescale.com>
5 * CREDITS: Kim Phillips contribute to LIBFDT code
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
17 #include <asm/fsl_mpc83xx_serdes.h>
18 #include <asm/fsl_enet.h>
19 #include <spd_sdram.h>
22 #include <fdt_support.h>
23 #include <fsl_esdhc.h>
26 #include "../common/pq-mds-pib.h"
28 int board_early_init_f(void)
30 u8 *bcsr = (u8 *)CONFIG_SYS_BCSR;
32 /* Enable flash write */
34 /* Clear all of the interrupt of BCSR */
37 #ifdef CONFIG_FSL_SERDES
38 immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
39 u32 spridr = in_be32(&immr->sysconf.spridr);
41 /* we check only part num, and don't look for CPU revisions */
42 switch (PARTID_NO_E(spridr)) {
44 fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA,
45 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
48 fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SGMII,
49 FSL_SERDES_CLK_125, FSL_SERDES_VDD_1V);
52 fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA,
53 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
54 fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_SATA,
55 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
58 printf("serdes not configured: unknown CPU part number: "
59 "%04x\n", spridr >> 16);
62 #endif /* CONFIG_FSL_SERDES */
66 #ifdef CONFIG_FSL_ESDHC
67 int board_mmc_init(bd_t *bd)
69 struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR;
70 u8 *bcsr = (u8 *)CONFIG_SYS_BCSR;
72 if (!hwconfig("esdhc"))
75 /* Set SPI_SD, SER_SD, and IRQ4_WP so that SD signals go through */
78 /* Set proper bits in SICR to allow SD signals through */
79 clrsetbits_be32(&im->sysconf.sicrl, SICRL_USB_B, SICRL_USB_B_SD);
80 clrsetbits_be32(&im->sysconf.sicrh, SICRH_GPIO2_E | SICRH_SPI,
81 SICRH_GPIO2_E_SD | SICRH_SPI_SD);
83 return fsl_esdhc_mmc_init(bd);
87 #if defined(CONFIG_TSEC1) || defined(CONFIG_TSEC2)
88 int board_eth_init(bd_t *bd)
90 struct fsl_pq_mdio_info mdio_info;
91 struct tsec_info_struct tsec_info[2];
92 struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR;
93 u32 rcwh = in_be32(&im->reset.rcwh);
97 /* New line after Net: */
101 SET_STD_TSEC_INFO(tsec_info[num], 1);
103 printf(CONFIG_TSEC1_NAME ": ");
105 tsec_mode = rcwh & HRCWH_TSEC1M_MASK;
106 if (tsec_mode == HRCWH_TSEC1M_IN_RGMII) {
108 /* this is default, no need to fixup */
109 } else if (tsec_mode == HRCWH_TSEC1M_IN_SGMII) {
111 tsec_info[num].phyaddr = TSEC1_PHY_ADDR_SGMII;
112 tsec_info[num].flags = TSEC_GIGABIT;
114 printf("unsupported PHY type\n");
119 SET_STD_TSEC_INFO(tsec_info[num], 2);
121 printf(CONFIG_TSEC2_NAME ": ");
123 tsec_mode = rcwh & HRCWH_TSEC2M_MASK;
124 if (tsec_mode == HRCWH_TSEC2M_IN_RGMII) {
126 /* this is default, no need to fixup */
127 } else if (tsec_mode == HRCWH_TSEC2M_IN_SGMII) {
129 tsec_info[num].phyaddr = TSEC2_PHY_ADDR_SGMII;
130 tsec_info[num].flags = TSEC_GIGABIT;
132 printf("unsupported PHY type\n");
137 mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
138 mdio_info.name = DEFAULT_MII_NAME;
139 fsl_pq_mdio_init(bd, &mdio_info);
141 return tsec_eth_init(bd, tsec_info, num);
144 static void __ft_tsec_fixup(void *blob, bd_t *bd, const char *alias,
151 off = fdt_path_offset(blob, alias);
153 printf("WARNING: could not find %s alias: %s.\n", alias,
158 err = fdt_fixup_phy_connection(blob, off, SGMII);
161 printf("WARNING: could not set phy-connection-type for %s: "
162 "%s.\n", alias, fdt_strerror(err));
166 ph = (u32 *)fdt_getprop(blob, off, "phy-handle", 0);
168 printf("WARNING: could not get phy-handle for %s.\n",
173 off = fdt_node_offset_by_phandle(blob, *ph);
175 printf("WARNING: could not get phy node for %s: %s\n", alias,
180 phy_addr = cpu_to_fdt32(phy_addr);
181 err = fdt_setprop(blob, off, "reg", &phy_addr, sizeof(phy_addr));
183 printf("WARNING: could not set phy node's reg for %s: "
184 "%s.\n", alias, fdt_strerror(err));
189 static void ft_tsec_fixup(void *blob, bd_t *bd)
191 struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR;
192 u32 rcwh = in_be32(&im->reset.rcwh);
196 tsec_mode = rcwh & HRCWH_TSEC1M_MASK;
197 if (tsec_mode == HRCWH_TSEC1M_IN_SGMII)
198 __ft_tsec_fixup(blob, bd, "ethernet0", TSEC1_PHY_ADDR_SGMII);
202 tsec_mode = rcwh & HRCWH_TSEC2M_MASK;
203 if (tsec_mode == HRCWH_TSEC2M_IN_SGMII)
204 __ft_tsec_fixup(blob, bd, "ethernet1", TSEC2_PHY_ADDR_SGMII);
208 static inline void ft_tsec_fixup(void *blob, bd_t *bd) {}
209 #endif /* defined(CONFIG_TSEC1) || defined(CONFIG_TSEC2) */
211 int board_early_init_r(void)
213 #ifdef CONFIG_PQ_MDS_PIB
219 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
220 extern void ddr_enable_ecc(unsigned int dram_size);
222 int fixed_sdram(void);
224 phys_size_t initdram(int board_type)
226 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
229 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
232 #if defined(CONFIG_SPD_EEPROM)
235 msize = fixed_sdram();
238 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
239 /* Initialize DDR ECC byte */
240 ddr_enable_ecc(msize * 1024 * 1024);
243 /* return total bus DDR size(bytes) */
244 return (msize * 1024 * 1024);
247 #if !defined(CONFIG_SPD_EEPROM)
248 /*************************************************************************
249 * fixed sdram init -- doesn't use serial presence detect.
250 ************************************************************************/
251 int fixed_sdram(void)
253 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
254 u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
255 u32 msize_log2 = __ilog2(msize);
257 im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
258 im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
260 #if (CONFIG_SYS_DDR_SIZE != 512)
261 #warning Currenly any ddr size other than 512 is not supported
263 im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
266 im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL;
269 im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
270 im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
273 im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
274 im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
275 im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
276 im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
277 im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
278 im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
279 im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
280 im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
281 im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
282 __asm__ __volatile__("sync");
285 im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
287 return CONFIG_SYS_DDR_SIZE;
289 #endif /*!CONFIG_SYS_SPD_EEPROM */
293 puts("Board: Freescale MPC837xEMDS\n");
298 int board_pci_host_broken(void)
300 struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR;
301 const u32 rcw_mask = HRCWH_PCI1_ARBITER_ENABLE | HRCWH_PCI_HOST;
303 /* It's always OK in case of external arbiter. */
304 if (hwconfig_subarg_cmp("pci", "arbiter", "external"))
307 if ((in_be32(&im->reset.rcwh) & rcw_mask) != rcw_mask)
313 static void ft_pci_fixup(void *blob, bd_t *bd)
315 const char *status = "broken (no arbiter)";
319 off = fdt_path_offset(blob, "pci0");
321 printf("WARNING: could not find pci0 alias: %s.\n",
326 err = fdt_setprop(blob, off, "status", status, strlen(status) + 1);
328 printf("WARNING: could not set status for pci0: %s.\n",
335 #if defined(CONFIG_OF_BOARD_SETUP)
336 void ft_board_setup(void *blob, bd_t *bd)
338 ft_cpu_setup(blob, bd);
339 ft_tsec_fixup(blob, bd);
340 fdt_fixup_dr_usb(blob, bd);
341 fdt_fixup_esdhc(blob, bd);
343 ft_pci_setup(blob, bd);
344 if (board_pci_host_broken())
345 ft_pci_fixup(blob, bd);
346 ft_pcie_fixup(blob, bd);
349 #endif /* CONFIG_OF_BOARD_SETUP */