2 * Copyright (C) 2007 Freescale Semiconductor, Inc.
3 * Dave Liu <daveliu@freescale.com>
5 * CREDITS: Kim Phillips contribute to LIBFDT code
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
16 #include <asm/fsl_serdes.h>
17 #include <spd_sdram.h>
19 #if defined(CONFIG_OF_LIBFDT)
22 #if defined(CONFIG_PQ_MDS_PIB)
23 #include "../common/pq-mds-pib.h"
26 int board_early_init_f(void)
28 u8 *bcsr = (u8 *)CONFIG_SYS_BCSR;
30 /* Enable flash write */
32 /* Clear all of the interrupt of BCSR */
35 #ifdef CONFIG_FSL_SERDES
36 immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
37 u32 spridr = in_be32(&immr->sysconf.spridr);
39 /* we check only part num, and don't look for CPU revisions */
40 switch (PARTID_NO_E(spridr)) {
42 fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA,
43 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
44 fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX,
45 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
48 fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SGMII,
49 FSL_SERDES_CLK_125, FSL_SERDES_VDD_1V);
50 fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX,
51 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
54 fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA,
55 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
56 fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_SATA,
57 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
60 printf("serdes not configured: unknown CPU part number: "
61 "%04x\n", spridr >> 16);
64 #endif /* CONFIG_FSL_SERDES */
68 #if defined(CONFIG_TSEC1) || defined(CONFIG_TSEC2)
69 int board_eth_init(bd_t *bd)
71 struct tsec_info_struct tsec_info[2];
72 struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR;
73 u32 rcwh = in_be32(&im->reset.rcwh);
77 /* New line after Net: */
81 SET_STD_TSEC_INFO(tsec_info[num], 1);
83 printf(CONFIG_TSEC1_NAME ": ");
85 tsec_mode = rcwh & HRCWH_TSEC1M_MASK;
86 if (tsec_mode == HRCWH_TSEC1M_IN_RGMII) {
88 /* this is default, no need to fixup */
89 } else if (tsec_mode == HRCWH_TSEC1M_IN_SGMII) {
91 tsec_info[num].phyaddr = TSEC1_PHY_ADDR_SGMII;
92 tsec_info[num].flags = TSEC_GIGABIT;
94 printf("unsupported PHY type\n");
99 SET_STD_TSEC_INFO(tsec_info[num], 2);
101 printf(CONFIG_TSEC2_NAME ": ");
103 tsec_mode = rcwh & HRCWH_TSEC2M_MASK;
104 if (tsec_mode == HRCWH_TSEC2M_IN_RGMII) {
106 /* this is default, no need to fixup */
107 } else if (tsec_mode == HRCWH_TSEC2M_IN_SGMII) {
109 tsec_info[num].phyaddr = TSEC2_PHY_ADDR_SGMII;
110 tsec_info[num].flags = TSEC_GIGABIT;
112 printf("unsupported PHY type\n");
116 return tsec_eth_init(bd, tsec_info, num);
119 static void __ft_tsec_fixup(void *blob, bd_t *bd, const char *alias,
122 const char *phy_type = "sgmii";
127 off = fdt_path_offset(blob, alias);
129 printf("WARNING: could not find %s alias: %s.\n", alias,
134 err = fdt_setprop(blob, off, "phy-connection-type", phy_type,
135 strlen(phy_type) + 1);
137 printf("WARNING: could not set phy-connection-type for %s: "
138 "%s.\n", alias, fdt_strerror(err));
142 ph = (u32 *)fdt_getprop(blob, off, "phy-handle", 0);
144 printf("WARNING: could not get phy-handle for %s.\n",
149 off = fdt_node_offset_by_phandle(blob, *ph);
151 printf("WARNING: could not get phy node for %s: %s\n", alias,
156 phy_addr = cpu_to_fdt32(phy_addr);
157 err = fdt_setprop(blob, off, "reg", &phy_addr, sizeof(phy_addr));
159 printf("WARNING: could not set phy node's reg for %s: "
160 "%s.\n", alias, fdt_strerror(err));
165 static void ft_tsec_fixup(void *blob, bd_t *bd)
167 struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR;
168 u32 rcwh = in_be32(&im->reset.rcwh);
172 tsec_mode = rcwh & HRCWH_TSEC1M_MASK;
173 if (tsec_mode == HRCWH_TSEC1M_IN_SGMII)
174 __ft_tsec_fixup(blob, bd, "ethernet0", TSEC1_PHY_ADDR_SGMII);
178 tsec_mode = rcwh & HRCWH_TSEC2M_MASK;
179 if (tsec_mode == HRCWH_TSEC2M_IN_SGMII)
180 __ft_tsec_fixup(blob, bd, "ethernet1", TSEC2_PHY_ADDR_SGMII);
184 static inline void ft_tsec_fixup(void *blob, bd_t *bd) {}
185 #endif /* defined(CONFIG_TSEC1) || defined(CONFIG_TSEC2) */
187 int board_early_init_r(void)
189 #ifdef CONFIG_PQ_MDS_PIB
195 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
196 extern void ddr_enable_ecc(unsigned int dram_size);
198 int fixed_sdram(void);
200 phys_size_t initdram(int board_type)
202 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
205 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
208 #if defined(CONFIG_SPD_EEPROM)
211 msize = fixed_sdram();
214 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
215 /* Initialize DDR ECC byte */
216 ddr_enable_ecc(msize * 1024 * 1024);
219 /* return total bus DDR size(bytes) */
220 return (msize * 1024 * 1024);
223 #if !defined(CONFIG_SPD_EEPROM)
224 /*************************************************************************
225 * fixed sdram init -- doesn't use serial presence detect.
226 ************************************************************************/
227 int fixed_sdram(void)
229 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
230 u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
231 u32 msize_log2 = __ilog2(msize);
233 im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
234 im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
236 #if (CONFIG_SYS_DDR_SIZE != 512)
237 #warning Currenly any ddr size other than 512 is not supported
239 im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
242 im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL;
245 im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
246 im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
249 im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
250 im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
251 im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
252 im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
253 im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
254 im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
255 im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
256 im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
257 im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
258 __asm__ __volatile__("sync");
261 im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
263 return CONFIG_SYS_DDR_SIZE;
265 #endif /*!CONFIG_SYS_SPD_EEPROM */
269 puts("Board: Freescale MPC837xEMDS\n");
274 int board_pci_host_broken(void)
276 struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR;
277 const u32 rcw_mask = HRCWH_PCI1_ARBITER_ENABLE | HRCWH_PCI_HOST;
278 const char *pci_ea = getenv("pci_external_arbiter");
280 /* It's always OK in case of external arbiter. */
281 if (pci_ea && !strcmp(pci_ea, "yes"))
284 if ((in_be32(&im->reset.rcwh) & rcw_mask) != rcw_mask)
290 static void ft_pci_fixup(void *blob, bd_t *bd)
292 const char *status = "broken (no arbiter)";
296 off = fdt_path_offset(blob, "pci0");
298 printf("WARNING: could not find pci0 alias: %s.\n",
303 err = fdt_setprop(blob, off, "status", status, strlen(status) + 1);
305 printf("WARNING: could not set status for pci0: %s.\n",
312 #if defined(CONFIG_OF_BOARD_SETUP)
313 void ft_board_setup(void *blob, bd_t *bd)
315 ft_cpu_setup(blob, bd);
316 ft_tsec_fixup(blob, bd);
318 ft_pci_setup(blob, bd);
319 if (board_pci_host_broken())
320 ft_pci_fixup(blob, bd);
323 #endif /* CONFIG_OF_BOARD_SETUP */