2 * Copyright (C) 2007 Freescale Semiconductor, Inc.
3 * Dave Liu <daveliu@freescale.com>
5 * CREDITS: Kim Phillips contribute to LIBFDT code
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
17 #include <asm/fsl_serdes.h>
18 #include <spd_sdram.h>
21 #include <fdt_support.h>
22 #include <fsl_esdhc.h>
24 #include "../common/pq-mds-pib.h"
26 int board_early_init_f(void)
28 u8 *bcsr = (u8 *)CONFIG_SYS_BCSR;
30 /* Enable flash write */
32 /* Clear all of the interrupt of BCSR */
35 #ifdef CONFIG_FSL_SERDES
36 immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
37 u32 spridr = in_be32(&immr->sysconf.spridr);
39 /* we check only part num, and don't look for CPU revisions */
40 switch (PARTID_NO_E(spridr)) {
42 fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA,
43 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
46 fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SGMII,
47 FSL_SERDES_CLK_125, FSL_SERDES_VDD_1V);
50 fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA,
51 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
52 fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_SATA,
53 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
56 printf("serdes not configured: unknown CPU part number: "
57 "%04x\n", spridr >> 16);
60 #endif /* CONFIG_FSL_SERDES */
64 #ifdef CONFIG_FSL_ESDHC
65 int board_mmc_init(bd_t *bd)
67 struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR;
68 u8 *bcsr = (u8 *)CONFIG_SYS_BCSR;
70 if (!hwconfig("esdhc"))
73 /* Set SPI_SD, SER_SD, and IRQ4_WP so that SD signals go through */
76 /* Set proper bits in SICR to allow SD signals through */
77 clrsetbits_be32(&im->sysconf.sicrl, SICRL_USB_B, SICRL_USB_B_SD);
78 clrsetbits_be32(&im->sysconf.sicrh, SICRH_GPIO2_E | SICRH_SPI,
79 SICRH_GPIO2_E_SD | SICRH_SPI_SD);
81 return fsl_esdhc_mmc_init(bd);
85 #if defined(CONFIG_TSEC1) || defined(CONFIG_TSEC2)
86 int board_eth_init(bd_t *bd)
88 struct tsec_info_struct tsec_info[2];
89 struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR;
90 u32 rcwh = in_be32(&im->reset.rcwh);
94 /* New line after Net: */
98 SET_STD_TSEC_INFO(tsec_info[num], 1);
100 printf(CONFIG_TSEC1_NAME ": ");
102 tsec_mode = rcwh & HRCWH_TSEC1M_MASK;
103 if (tsec_mode == HRCWH_TSEC1M_IN_RGMII) {
105 /* this is default, no need to fixup */
106 } else if (tsec_mode == HRCWH_TSEC1M_IN_SGMII) {
108 tsec_info[num].phyaddr = TSEC1_PHY_ADDR_SGMII;
109 tsec_info[num].flags = TSEC_GIGABIT;
111 printf("unsupported PHY type\n");
116 SET_STD_TSEC_INFO(tsec_info[num], 2);
118 printf(CONFIG_TSEC2_NAME ": ");
120 tsec_mode = rcwh & HRCWH_TSEC2M_MASK;
121 if (tsec_mode == HRCWH_TSEC2M_IN_RGMII) {
123 /* this is default, no need to fixup */
124 } else if (tsec_mode == HRCWH_TSEC2M_IN_SGMII) {
126 tsec_info[num].phyaddr = TSEC2_PHY_ADDR_SGMII;
127 tsec_info[num].flags = TSEC_GIGABIT;
129 printf("unsupported PHY type\n");
133 return tsec_eth_init(bd, tsec_info, num);
136 static void __ft_tsec_fixup(void *blob, bd_t *bd, const char *alias,
139 const char *phy_type = "sgmii";
144 off = fdt_path_offset(blob, alias);
146 printf("WARNING: could not find %s alias: %s.\n", alias,
151 err = fdt_setprop(blob, off, "phy-connection-type", phy_type,
152 strlen(phy_type) + 1);
154 printf("WARNING: could not set phy-connection-type for %s: "
155 "%s.\n", alias, fdt_strerror(err));
159 ph = (u32 *)fdt_getprop(blob, off, "phy-handle", 0);
161 printf("WARNING: could not get phy-handle for %s.\n",
166 off = fdt_node_offset_by_phandle(blob, *ph);
168 printf("WARNING: could not get phy node for %s: %s\n", alias,
173 phy_addr = cpu_to_fdt32(phy_addr);
174 err = fdt_setprop(blob, off, "reg", &phy_addr, sizeof(phy_addr));
176 printf("WARNING: could not set phy node's reg for %s: "
177 "%s.\n", alias, fdt_strerror(err));
182 static void ft_tsec_fixup(void *blob, bd_t *bd)
184 struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR;
185 u32 rcwh = in_be32(&im->reset.rcwh);
189 tsec_mode = rcwh & HRCWH_TSEC1M_MASK;
190 if (tsec_mode == HRCWH_TSEC1M_IN_SGMII)
191 __ft_tsec_fixup(blob, bd, "ethernet0", TSEC1_PHY_ADDR_SGMII);
195 tsec_mode = rcwh & HRCWH_TSEC2M_MASK;
196 if (tsec_mode == HRCWH_TSEC2M_IN_SGMII)
197 __ft_tsec_fixup(blob, bd, "ethernet1", TSEC2_PHY_ADDR_SGMII);
201 static inline void ft_tsec_fixup(void *blob, bd_t *bd) {}
202 #endif /* defined(CONFIG_TSEC1) || defined(CONFIG_TSEC2) */
204 int board_early_init_r(void)
206 #ifdef CONFIG_PQ_MDS_PIB
212 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
213 extern void ddr_enable_ecc(unsigned int dram_size);
215 int fixed_sdram(void);
217 phys_size_t initdram(int board_type)
219 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
222 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
225 #if defined(CONFIG_SPD_EEPROM)
228 msize = fixed_sdram();
231 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
232 /* Initialize DDR ECC byte */
233 ddr_enable_ecc(msize * 1024 * 1024);
236 /* return total bus DDR size(bytes) */
237 return (msize * 1024 * 1024);
240 #if !defined(CONFIG_SPD_EEPROM)
241 /*************************************************************************
242 * fixed sdram init -- doesn't use serial presence detect.
243 ************************************************************************/
244 int fixed_sdram(void)
246 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
247 u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
248 u32 msize_log2 = __ilog2(msize);
250 im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
251 im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
253 #if (CONFIG_SYS_DDR_SIZE != 512)
254 #warning Currenly any ddr size other than 512 is not supported
256 im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
259 im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL;
262 im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
263 im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
266 im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
267 im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
268 im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
269 im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
270 im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
271 im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
272 im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
273 im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
274 im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
275 __asm__ __volatile__("sync");
278 im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
280 return CONFIG_SYS_DDR_SIZE;
282 #endif /*!CONFIG_SYS_SPD_EEPROM */
286 puts("Board: Freescale MPC837xEMDS\n");
291 int board_pci_host_broken(void)
293 struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR;
294 const u32 rcw_mask = HRCWH_PCI1_ARBITER_ENABLE | HRCWH_PCI_HOST;
295 const char *pci_ea = getenv("pci_external_arbiter");
297 /* It's always OK in case of external arbiter. */
298 if (pci_ea && !strcmp(pci_ea, "yes"))
301 if ((in_be32(&im->reset.rcwh) & rcw_mask) != rcw_mask)
307 static void ft_pci_fixup(void *blob, bd_t *bd)
309 const char *status = "broken (no arbiter)";
313 off = fdt_path_offset(blob, "pci0");
315 printf("WARNING: could not find pci0 alias: %s.\n",
320 err = fdt_setprop(blob, off, "status", status, strlen(status) + 1);
322 printf("WARNING: could not set status for pci0: %s.\n",
329 #if defined(CONFIG_OF_BOARD_SETUP)
330 void ft_board_setup(void *blob, bd_t *bd)
332 ft_cpu_setup(blob, bd);
333 ft_tsec_fixup(blob, bd);
334 fdt_fixup_dr_usb(blob, bd);
335 fdt_fixup_esdhc(blob, bd);
337 ft_pci_setup(blob, bd);
338 if (board_pci_host_broken())
339 ft_pci_fixup(blob, bd);
340 ft_pcie_fixup(blob, bd);
343 #endif /* CONFIG_OF_BOARD_SETUP */