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[u-boot] / board / freescale / mpc837xerdb / mpc837xerdb.c
1 /*
2  * Copyright (C) 2007 Freescale Semiconductor, Inc.
3  * Kevin Lam <kevin.lam@freescale.com>
4  * Joe D'Abbraccio <joe.d'abbraccio@freescale.com>
5  *
6  * See file CREDITS for list of people who contributed to this
7  * project.
8  *
9  * This program is free software; you can redistribute it and/or
10  * modify it under the terms of the GNU General Public License as
11  * published by the Free Software Foundation; either version 2 of
12  * the License, or (at your option) any later version.
13  */
14
15 #include <common.h>
16 #include <hwconfig.h>
17 #include <i2c.h>
18 #include <asm/io.h>
19 #include <asm/fsl_mpc83xx_serdes.h>
20 #include <fdt_support.h>
21 #include <spd_sdram.h>
22 #include <vsc7385.h>
23 #include <fsl_esdhc.h>
24
25 #if defined(CONFIG_SYS_DRAM_TEST)
26 int
27 testdram(void)
28 {
29         uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
30         uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
31         uint *p;
32
33         printf("Testing DRAM from 0x%08x to 0x%08x\n",
34                CONFIG_SYS_MEMTEST_START,
35                CONFIG_SYS_MEMTEST_END);
36
37         printf("DRAM test phase 1:\n");
38         for (p = pstart; p < pend; p++)
39                 *p = 0xaaaaaaaa;
40
41         for (p = pstart; p < pend; p++) {
42                 if (*p != 0xaaaaaaaa) {
43                         printf("DRAM test fails at: %08x\n", (uint) p);
44                         return 1;
45                 }
46         }
47
48         printf("DRAM test phase 2:\n");
49         for (p = pstart; p < pend; p++)
50                 *p = 0x55555555;
51
52         for (p = pstart; p < pend; p++) {
53                 if (*p != 0x55555555) {
54                         printf("DRAM test fails at: %08x\n", (uint) p);
55                         return 1;
56                 }
57         }
58
59         printf("DRAM test passed.\n");
60         return 0;
61 }
62 #endif
63
64 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
65 void ddr_enable_ecc(unsigned int dram_size);
66 #endif
67 int fixed_sdram(void);
68
69 phys_size_t initdram(int board_type)
70 {
71         immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
72         u32 msize = 0;
73
74         if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
75                 return -1;
76
77 #if defined(CONFIG_SPD_EEPROM)
78         msize = spd_sdram();
79 #else
80         msize = fixed_sdram();
81 #endif
82
83 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
84         /* Initialize DDR ECC byte */
85         ddr_enable_ecc(msize * 1024 * 1024);
86 #endif
87         /* return total bus DDR size(bytes) */
88         return (msize * 1024 * 1024);
89 }
90
91 #if !defined(CONFIG_SPD_EEPROM)
92 /*************************************************************************
93  *  fixed sdram init -- doesn't use serial presence detect.
94  ************************************************************************/
95 int fixed_sdram(void)
96 {
97         immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
98         u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
99         u32 msize_log2 = __ilog2(msize);
100
101         im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
102         im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
103
104         im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
105         udelay(50000);
106
107         im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL;
108         udelay(1000);
109
110         im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
111         im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
112         udelay(1000);
113
114         im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
115         im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
116         im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
117         im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
118         im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
119         im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
120         im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
121         im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
122         im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
123         sync();
124         udelay(1000);
125
126         im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
127         udelay(2000);
128         return CONFIG_SYS_DDR_SIZE;
129 }
130 #endif  /*!CONFIG_SYS_SPD_EEPROM */
131
132 int checkboard(void)
133 {
134         puts("Board: Freescale MPC837xERDB\n");
135         return 0;
136 }
137
138 int board_early_init_f(void)
139 {
140 #ifdef CONFIG_FSL_SERDES
141         immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
142         u32 spridr = in_be32(&immr->sysconf.spridr);
143
144         /* we check only part num, and don't look for CPU revisions */
145         switch (PARTID_NO_E(spridr)) {
146         case SPR_8377:
147                 fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA,
148                                  FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
149                 fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX,
150                                  FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
151                 break;
152         case SPR_8378:
153                 fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX,
154                                  FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
155                 break;
156         case SPR_8379:
157                 fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA,
158                                  FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
159                 fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_SATA,
160                                  FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
161                 break;
162         default:
163                 printf("serdes not configured: unknown CPU part number: "
164                        "%04x\n", spridr >> 16);
165                 break;
166         }
167 #endif /* CONFIG_FSL_SERDES */
168         return 0;
169 }
170
171 #ifdef CONFIG_FSL_ESDHC
172 int board_mmc_init(bd_t *bd)
173 {
174         struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR;
175
176         if (!hwconfig("esdhc"))
177                 return 0;
178
179         clrsetbits_be32(&im->sysconf.sicrl, SICRL_USB_B, SICRL_USB_B_SD);
180         clrsetbits_be32(&im->sysconf.sicrh, SICRH_SPI, SICRH_SPI_SD);
181
182         return fsl_esdhc_mmc_init(bd);
183 }
184 #endif
185
186 /*
187  * Miscellaneous late-boot configurations
188  *
189  * If a VSC7385 microcode image is present, then upload it.
190 */
191 int misc_init_r(void)
192 {
193         int rc = 0;
194
195 #ifdef CONFIG_VSC7385_IMAGE
196         if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE,
197                 CONFIG_VSC7385_IMAGE_SIZE)) {
198                 puts("Failure uploading VSC7385 microcode.\n");
199                 rc = 1;
200         }
201 #endif
202
203         return rc;
204 }
205
206 #if defined(CONFIG_OF_BOARD_SETUP)
207
208 void ft_board_setup(void *blob, bd_t *bd)
209 {
210 #ifdef CONFIG_PCI
211         ft_pci_setup(blob, bd);
212 #endif
213         ft_cpu_setup(blob, bd);
214         fdt_fixup_dr_usb(blob, bd);
215         fdt_fixup_esdhc(blob, bd);
216 }
217 #endif /* CONFIG_OF_BOARD_SETUP */