2 * Copyright 2008-2010 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/processor.h>
28 #include <asm/cache.h>
29 #include <asm/immap_85xx.h>
30 #include <asm/fsl_pci.h>
31 #include <asm/fsl_ddr_sdram.h>
33 #include <asm/fsl_serdes.h>
37 #include <spd_sdram.h>
38 #include <fdt_support.h>
43 #include "../common/sgmii_riser.h"
45 phys_size_t fixed_sdram(void);
47 int board_early_init_f (void)
50 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
52 setbits_be32(&gur->pmuxcr,
53 (MPC85xx_PMUXCR_SD_DATA |
54 MPC85xx_PMUXCR_SDHC_CD |
55 MPC85xx_PMUXCR_SDHC_WP));
64 u8 *pixis_base = (u8 *)PIXIS_BASE;
66 puts("Board: MPC8536DS ");
67 #ifdef CONFIG_PHYS_64BIT
68 puts("(36-bit addrmap) ");
71 printf ("Sys ID: 0x%02x, "
72 "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
73 in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
74 in_8(pixis_base + PIXIS_PVER));
76 vboot = in_8(pixis_base + PIXIS_VBOOT);
77 switch ((vboot & PIXIS_VBOOT_LBMAP) >> 5) {
78 case PIXIS_VBOOT_LBMAP_NOR0:
81 case PIXIS_VBOOT_LBMAP_NOR1:
84 case PIXIS_VBOOT_LBMAP_NOR2:
87 case PIXIS_VBOOT_LBMAP_NOR3:
90 case PIXIS_VBOOT_LBMAP_PJET:
93 case PIXIS_VBOOT_LBMAP_NAND:
102 initdram(int board_type)
104 phys_size_t dram_size = 0;
106 puts("Initializing....");
108 #ifdef CONFIG_SPD_EEPROM
109 dram_size = fsl_ddr_sdram();
111 dram_size = fixed_sdram();
113 dram_size = setup_ddr_tlbs(dram_size / 0x100000);
114 dram_size *= 0x100000;
120 #if !defined(CONFIG_SPD_EEPROM)
122 * Fixed sdram init -- doesn't use serial presence detect.
125 phys_size_t fixed_sdram (void)
127 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
128 volatile ccsr_ddr_t *ddr= &immap->im_ddr;
131 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
132 ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
134 ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
135 ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
136 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
137 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
138 ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
139 ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
140 ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
141 ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
142 ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
143 ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;
145 #if defined (CONFIG_DDR_ECC)
146 ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN;
147 ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS;
148 ddr->err_sbe = CONFIG_SYS_DDR_SBE;
154 ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
156 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
158 debug("DDR - 1st controller: memory initializing\n");
160 * Poll until memory is initialized.
161 * 512 Meg at 400 might hit this 200 times or so.
163 while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) {
166 debug("DDR: memory initialized\n\n");
171 return 512 * 1024 * 1024;
177 static struct pci_controller pci1_hose;
181 static struct pci_controller pcie1_hose;
185 static struct pci_controller pcie2_hose;
189 static struct pci_controller pcie3_hose;
193 void pci_init_board(void)
195 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
196 struct fsl_pci_info pci_info[4];
197 u32 devdisr, pordevsr, io_sel, sdrs2_io_sel;
198 u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel;
199 int first_free_busno = 0;
202 int pcie_ep, pcie_configured;
204 devdisr = in_be32(&gur->devdisr);
205 pordevsr = in_be32(&gur->pordevsr);
206 porpllsr = in_be32(&gur->porpllsr);
207 io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
208 sdrs2_io_sel = (pordevsr & MPC85xx_PORDEVSR_SRDS2_IO_SEL) >> 27;
210 debug(" pci_init_board: devdisr=%x, sdrs2_io_sel=%x, io_sel=%x\n",
211 devdisr, sdrs2_io_sel, io_sel);
213 if (sdrs2_io_sel == 7)
214 printf(" Serdes2 disalbed\n");
215 else if (sdrs2_io_sel == 4) {
216 printf(" eTSEC1 is in sgmii mode.\n");
217 printf(" eTSEC3 is in sgmii mode.\n");
218 } else if (sdrs2_io_sel == 6)
219 printf(" eTSEC1 is in sgmii mode.\n");
223 pcie_configured = is_serdes_configured(PCIE3);
225 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)){
226 set_next_law(CONFIG_SYS_PCIE3_MEM_PHYS, LAW_SIZE_512M,
228 set_next_law(CONFIG_SYS_PCIE3_IO_PHYS, LAW_SIZE_64K,
230 SET_STD_PCIE_INFO(pci_info[num], 3);
231 pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info[num].regs);
232 printf (" PCIE3 connected to Slot3 as %s (base address %lx)\n",
233 pcie_ep ? "Endpoint" : "Root Complex",
235 first_free_busno = fsl_pci_init_port(&pci_info[num++],
236 &pcie3_hose, first_free_busno);
238 printf (" PCIE3: disabled\n");
243 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE3); /* disable */
247 pcie_configured = is_serdes_configured(PCIE1);
249 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
250 set_next_law(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_128M,
252 set_next_law(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_64K,
254 SET_STD_PCIE_INFO(pci_info[num], 1);
255 pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
256 printf (" PCIE1 connected to Slot1 as %s (base address %lx)\n",
257 pcie_ep ? "Endpoint" : "Root Complex",
259 first_free_busno = fsl_pci_init_port(&pci_info[num++],
260 &pcie1_hose, first_free_busno);
262 printf (" PCIE1: disabled\n");
267 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */
271 pcie_configured = is_serdes_configured(PCIE2);
273 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)){
274 set_next_law(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_128M,
276 set_next_law(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_64K,
278 SET_STD_PCIE_INFO(pci_info[num], 2);
279 pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
280 printf (" PCIE2 connected to Slot 2 as %s (base address %lx)\n",
281 pcie_ep ? "Endpoint" : "Root Complex",
283 first_free_busno = fsl_pci_init_port(&pci_info[num++],
284 &pcie2_hose, first_free_busno);
286 printf (" PCIE2: disabled\n");
291 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE2); /* disable */
295 pci_speed = 66666000;
297 pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
298 pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
300 if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
301 set_next_law(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_256M,
303 set_next_law(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_64K,
305 SET_STD_PCI_INFO(pci_info[num], 1);
306 pci_agent = fsl_setup_hose(&pci1_hose, pci_info[num].regs);
307 printf ("\n PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
309 (pci_speed == 33333000) ? "33" :
310 (pci_speed == 66666000) ? "66" : "unknown",
311 pci_clk_sel ? "sync" : "async",
312 pci_agent ? "agent" : "host",
313 pci_arb ? "arbiter" : "external-arbiter",
316 first_free_busno = fsl_pci_init_port(&pci_info[num++],
317 &pci1_hose, first_free_busno);
319 printf (" PCI: disabled\n");
324 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */
329 int board_early_init_r(void)
331 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
332 const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
335 * Remap Boot flash + PROMJET region to caching-inhibited
336 * so that flash can be erased properly.
339 /* Flush d-cache and invalidate i-cache of any FLASH data */
343 /* invalidate existing TLB entry for flash + promjet */
344 disable_tlb(flash_esel);
346 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */
347 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */
348 0, flash_esel, BOOKE_PAGESZ_256M, 1); /* ts, esel, tsize, iprot */
353 int board_eth_init(bd_t *bis)
355 #ifdef CONFIG_TSEC_ENET
356 struct tsec_info_struct tsec_info[2];
357 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
360 (gur->pordevsr & MPC85xx_PORDEVSR_SRDS2_IO_SEL) >> 27;
363 SET_STD_TSEC_INFO(tsec_info[num], 1);
364 if ((sdrs2_io_sel == 4) || (sdrs2_io_sel == 6)) {
365 tsec_info[num].phyaddr = 0;
366 tsec_info[num].flags |= TSEC_SGMII;
371 SET_STD_TSEC_INFO(tsec_info[num], 3);
372 if (sdrs2_io_sel == 4) {
373 tsec_info[num].phyaddr = 1;
374 tsec_info[num].flags |= TSEC_SGMII;
380 printf("No TSECs initialized\n");
384 #ifdef CONFIG_FSL_SGMII_RISER
385 if ((sdrs2_io_sel == 4) || (sdrs2_io_sel == 6))
386 fsl_sgmii_riser_init(tsec_info, num);
389 tsec_eth_init(bis, tsec_info, num);
391 return pci_eth_init(bis);
394 #if defined(CONFIG_OF_BOARD_SETUP)
395 void ft_board_setup(void *blob, bd_t *bd)
397 ft_cpu_setup(blob, bd);
401 #ifdef CONFIG_FSL_SGMII_RISER
402 fsl_sgmii_riser_fdt_fixup(blob);