2 * Copyright 2008-2010 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/processor.h>
28 #include <asm/cache.h>
29 #include <asm/immap_85xx.h>
30 #include <asm/fsl_pci.h>
31 #include <asm/fsl_ddr_sdram.h>
33 #include <asm/fsl_serdes.h>
37 #include <spd_sdram.h>
38 #include <fdt_support.h>
43 #include "../common/sgmii_riser.h"
45 int board_early_init_f (void)
48 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
50 setbits_be32(&gur->pmuxcr,
51 (MPC85xx_PMUXCR_SD_DATA |
52 MPC85xx_PMUXCR_SDHC_CD |
53 MPC85xx_PMUXCR_SDHC_WP));
62 u8 *pixis_base = (u8 *)PIXIS_BASE;
64 puts("Board: MPC8536DS ");
65 #ifdef CONFIG_PHYS_64BIT
66 puts("(36-bit addrmap) ");
69 printf ("Sys ID: 0x%02x, "
70 "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
71 in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
72 in_8(pixis_base + PIXIS_PVER));
74 vboot = in_8(pixis_base + PIXIS_VBOOT);
75 switch ((vboot & PIXIS_VBOOT_LBMAP) >> 5) {
76 case PIXIS_VBOOT_LBMAP_NOR0:
79 case PIXIS_VBOOT_LBMAP_NOR1:
82 case PIXIS_VBOOT_LBMAP_NOR2:
85 case PIXIS_VBOOT_LBMAP_NOR3:
88 case PIXIS_VBOOT_LBMAP_PJET:
91 case PIXIS_VBOOT_LBMAP_NAND:
99 #if !defined(CONFIG_SPD_EEPROM)
101 * Fixed sdram init -- doesn't use serial presence detect.
104 phys_size_t fixed_sdram (void)
106 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
107 volatile ccsr_ddr_t *ddr= &immap->im_ddr;
110 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
111 ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
113 ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
114 ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
115 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
116 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
117 ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
118 ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
119 ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
120 ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
121 ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
122 ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;
124 #if defined (CONFIG_DDR_ECC)
125 ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN;
126 ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS;
127 ddr->err_sbe = CONFIG_SYS_DDR_SBE;
133 ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
135 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
137 debug("DDR - 1st controller: memory initializing\n");
139 * Poll until memory is initialized.
140 * 512 Meg at 400 might hit this 200 times or so.
142 while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) {
145 debug("DDR: memory initialized\n\n");
150 return 512 * 1024 * 1024;
156 static struct pci_controller pci1_hose;
160 void pci_init_board(void)
162 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
163 struct fsl_pci_info pci_info;
164 u32 devdisr, pordevsr;
165 u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel;
166 int first_free_busno;
168 first_free_busno = fsl_pcie_init_board(0);
171 devdisr = in_be32(&gur->devdisr);
172 pordevsr = in_be32(&gur->pordevsr);
173 porpllsr = in_be32(&gur->porpllsr);
175 pci_speed = 66666000;
177 pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
178 pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
180 if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
181 SET_STD_PCI_INFO(pci_info, 1);
182 set_next_law(pci_info.mem_phys,
183 law_size_bits(pci_info.mem_size), pci_info.law);
184 set_next_law(pci_info.io_phys,
185 law_size_bits(pci_info.io_size), pci_info.law);
187 pci_agent = fsl_setup_hose(&pci1_hose, pci_info.regs);
188 printf("PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
190 (pci_speed == 33333000) ? "33" :
191 (pci_speed == 66666000) ? "66" : "unknown",
192 pci_clk_sel ? "sync" : "async",
193 pci_agent ? "agent" : "host",
194 pci_arb ? "arbiter" : "external-arbiter",
197 first_free_busno = fsl_pci_init_port(&pci_info,
198 &pci1_hose, first_free_busno);
200 printf("PCI: disabled\n");
205 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */
210 int board_early_init_r(void)
212 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
213 const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
216 * Remap Boot flash + PROMJET region to caching-inhibited
217 * so that flash can be erased properly.
220 /* Flush d-cache and invalidate i-cache of any FLASH data */
224 /* invalidate existing TLB entry for flash + promjet */
225 disable_tlb(flash_esel);
227 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */
228 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */
229 0, flash_esel, BOOKE_PAGESZ_256M, 1); /* ts, esel, tsize, iprot */
234 int board_eth_init(bd_t *bis)
236 #ifdef CONFIG_TSEC_ENET
237 struct tsec_info_struct tsec_info[2];
241 SET_STD_TSEC_INFO(tsec_info[num], 1);
242 if (is_serdes_configured(SGMII_TSEC1)) {
243 puts("eTSEC1 is in sgmii mode.\n");
244 tsec_info[num].phyaddr = 0;
245 tsec_info[num].flags |= TSEC_SGMII;
250 SET_STD_TSEC_INFO(tsec_info[num], 3);
251 if (is_serdes_configured(SGMII_TSEC3)) {
252 puts("eTSEC3 is in sgmii mode.\n");
253 tsec_info[num].phyaddr = 1;
254 tsec_info[num].flags |= TSEC_SGMII;
260 printf("No TSECs initialized\n");
264 #ifdef CONFIG_FSL_SGMII_RISER
265 if (is_serdes_configured(SGMII_TSEC1) ||
266 is_serdes_configured(SGMII_TSEC3)) {
267 fsl_sgmii_riser_init(tsec_info, num);
271 tsec_eth_init(bis, tsec_info, num);
273 return pci_eth_init(bis);
276 #if defined(CONFIG_OF_BOARD_SETUP)
277 void ft_board_setup(void *blob, bd_t *bd)
279 ft_cpu_setup(blob, bd);
283 #ifdef CONFIG_FSL_SGMII_RISER
284 fsl_sgmii_riser_fdt_fixup(blob);