2 * Copyright 2008 Freescale Semiconductor.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/processor.h>
28 #include <asm/cache.h>
29 #include <asm/immap_85xx.h>
30 #include <asm/immap_fsl_pci.h>
31 #include <asm/fsl_ddr_sdram.h>
36 #include <spd_sdram.h>
37 #include <fdt_support.h>
41 #include "../common/pixis.h"
42 #include "../common/sgmii_riser.h"
44 phys_size_t fixed_sdram(void);
48 printf ("Board: MPC8536DS, System ID: 0x%02x, "
49 "System Version: 0x%02x, FPGA Version: 0x%02x\n",
50 in8(PIXIS_BASE + PIXIS_ID), in8(PIXIS_BASE + PIXIS_VER),
51 in8(PIXIS_BASE + PIXIS_PVER));
56 initdram(int board_type)
58 phys_size_t dram_size = 0;
60 puts("Initializing....");
62 #ifdef CONFIG_SPD_EEPROM
63 dram_size = fsl_ddr_sdram();
65 dram_size = fixed_sdram();
67 dram_size = setup_ddr_tlbs(dram_size / 0x100000);
68 dram_size *= 0x100000;
74 #if !defined(CONFIG_SPD_EEPROM)
76 * Fixed sdram init -- doesn't use serial presence detect.
79 phys_size_t fixed_sdram (void)
81 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
82 volatile ccsr_ddr_t *ddr= &immap->im_ddr;
85 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
86 ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
88 ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
89 ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
90 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
91 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
92 ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
93 ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
94 ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
95 ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
96 ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
97 ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;
99 #if defined (CONFIG_DDR_ECC)
100 ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN;
101 ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS;
102 ddr->err_sbe = CONFIG_SYS_DDR_SBE;
108 ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
110 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
112 debug("DDR - 1st controller: memory initializing\n");
114 * Poll until memory is initialized.
115 * 512 Meg at 400 might hit this 200 times or so.
117 while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) {
120 debug("DDR: memory initialized\n\n");
125 return 512 * 1024 * 1024;
131 static struct pci_controller pci1_hose;
135 static struct pci_controller pcie1_hose;
139 static struct pci_controller pcie2_hose;
143 static struct pci_controller pcie3_hose;
146 extern int fsl_pci_setup_inbound_windows(struct pci_region *r);
147 extern void fsl_pci_init(struct pci_controller *hose);
149 int first_free_busno=0;
154 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
155 uint devdisr = gur->devdisr;
157 (gur->pordevsr & MPC85xx_PORDEVSR_SRDS2_IO_SEL) >> 27;
158 uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
159 uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
161 debug(" pci_init_board: devdisr=%x, sdrs2_io_sel=%x, io_sel=%x,\
162 host_agent=%x\n", devdisr, sdrs2_io_sel, io_sel, host_agent);
164 if (sdrs2_io_sel == 7)
165 printf(" Serdes2 disalbed\n");
166 else if (sdrs2_io_sel == 4) {
167 printf(" eTSEC1 is in sgmii mode.\n");
168 printf(" eTSEC3 is in sgmii mode.\n");
169 } else if (sdrs2_io_sel == 6)
170 printf(" eTSEC1 is in sgmii mode.\n");
174 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE3_ADDR;
175 struct pci_controller *hose = &pcie3_hose;
176 int pcie_ep = (host_agent == 1);
177 int pcie_configured = (io_sel == 7);
178 struct pci_region *r = hose->regions;
180 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
181 printf ("\n PCIE3 connected to Slot3 as %s (base address %x)",
182 pcie_ep ? "End Point" : "Root Complex",
184 if (pci->pme_msg_det) {
185 pci->pme_msg_det = 0xffffffff;
186 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
191 r += fsl_pci_setup_inbound_windows(r);
193 /* outbound memory */
195 CONFIG_SYS_PCIE3_MEM_BASE,
196 CONFIG_SYS_PCIE3_MEM_PHYS,
197 CONFIG_SYS_PCIE3_MEM_SIZE,
202 CONFIG_SYS_PCIE3_IO_BASE,
203 CONFIG_SYS_PCIE3_IO_PHYS,
204 CONFIG_SYS_PCIE3_IO_SIZE,
207 hose->region_count = r - hose->regions;
209 hose->first_busno=first_free_busno;
210 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
214 first_free_busno=hose->last_busno+1;
215 printf (" PCIE3 on bus %02x - %02x\n",
216 hose->first_busno,hose->last_busno);
218 printf (" PCIE3: disabled\n");
223 gur->devdisr |= MPC85xx_DEVDISR_PCIE3; /* disable */
228 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
229 struct pci_controller *hose = &pcie1_hose;
230 int pcie_ep = (host_agent == 5);
231 int pcie_configured = (io_sel == 2 || io_sel == 3
232 || io_sel == 5 || io_sel == 7);
233 struct pci_region *r = hose->regions;
235 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
236 printf ("\n PCIE1 connected to Slot1 as %s (base address %x)",
237 pcie_ep ? "End Point" : "Root Complex",
239 if (pci->pme_msg_det) {
240 pci->pme_msg_det = 0xffffffff;
241 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
246 r += fsl_pci_setup_inbound_windows(r);
248 /* outbound memory */
250 CONFIG_SYS_PCIE1_MEM_BASE,
251 CONFIG_SYS_PCIE1_MEM_PHYS,
252 CONFIG_SYS_PCIE1_MEM_SIZE,
257 CONFIG_SYS_PCIE1_IO_BASE,
258 CONFIG_SYS_PCIE1_IO_PHYS,
259 CONFIG_SYS_PCIE1_IO_SIZE,
262 #ifdef CONFIG_SYS_PCIE1_MEM_BASE2
263 /* outbound memory */
265 CONFIG_SYS_PCIE1_MEM_BASE2,
266 CONFIG_SYS_PCIE1_MEM_PHYS2,
267 CONFIG_SYS_PCIE1_MEM_SIZE2,
270 hose->region_count = r - hose->regions;
271 hose->first_busno=first_free_busno;
273 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
277 first_free_busno=hose->last_busno+1;
278 printf(" PCIE1 on bus %02x - %02x\n",
279 hose->first_busno,hose->last_busno);
282 printf (" PCIE1: disabled\n");
287 gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
292 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR;
293 struct pci_controller *hose = &pcie2_hose;
294 int pcie_ep = (host_agent == 3);
295 int pcie_configured = (io_sel == 5 || io_sel == 7);
296 struct pci_region *r = hose->regions;
298 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
299 printf ("\n PCIE2 connected to Slot 2 as %s (base address %x)",
300 pcie_ep ? "End Point" : "Root Complex",
302 if (pci->pme_msg_det) {
303 pci->pme_msg_det = 0xffffffff;
304 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
309 r += fsl_pci_setup_inbound_windows(r);
311 /* outbound memory */
313 CONFIG_SYS_PCIE2_MEM_BASE,
314 CONFIG_SYS_PCIE2_MEM_PHYS,
315 CONFIG_SYS_PCIE2_MEM_SIZE,
320 CONFIG_SYS_PCIE2_IO_BASE,
321 CONFIG_SYS_PCIE2_IO_PHYS,
322 CONFIG_SYS_PCIE2_IO_SIZE,
325 #ifdef CONFIG_SYS_PCIE2_MEM_BASE2
326 /* outbound memory */
328 CONFIG_SYS_PCIE2_MEM_BASE2,
329 CONFIG_SYS_PCIE2_MEM_PHYS2,
330 CONFIG_SYS_PCIE2_MEM_SIZE2,
333 hose->region_count = r - hose->regions;
334 hose->first_busno=first_free_busno;
335 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
338 first_free_busno=hose->last_busno+1;
339 printf (" PCIE2 on bus %02x - %02x\n",
340 hose->first_busno,hose->last_busno);
343 printf (" PCIE2: disabled\n");
348 gur->devdisr |= MPC85xx_DEVDISR_PCIE2; /* disable */
354 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR;
355 struct pci_controller *hose = &pci1_hose;
356 struct pci_region *r = hose->regions;
358 uint pci_agent = (host_agent == 6);
359 uint pci_speed = 66666000; /*get_clock_freq (); PCI PSPEED in [4:5] */
361 uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */
362 uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */
365 if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
366 printf ("\n PCI: %d bit, %s MHz, %s, %s, %s (base address %x)\n",
368 (pci_speed == 33333000) ? "33" :
369 (pci_speed == 66666000) ? "66" : "unknown",
370 pci_clk_sel ? "sync" : "async",
371 pci_agent ? "agent" : "host",
372 pci_arb ? "arbiter" : "external-arbiter",
377 r += fsl_pci_setup_inbound_windows(r);
379 /* outbound memory */
381 CONFIG_SYS_PCI1_MEM_BASE,
382 CONFIG_SYS_PCI1_MEM_PHYS,
383 CONFIG_SYS_PCI1_MEM_SIZE,
388 CONFIG_SYS_PCI1_IO_BASE,
389 CONFIG_SYS_PCI1_IO_PHYS,
390 CONFIG_SYS_PCI1_IO_SIZE,
393 #ifdef CONFIG_SYS_PCI1_MEM_BASE2
394 /* outbound memory */
396 CONFIG_SYS_PCI1_MEM_BASE2,
397 CONFIG_SYS_PCI1_MEM_PHYS2,
398 CONFIG_SYS_PCI1_MEM_SIZE2,
401 hose->region_count = r - hose->regions;
402 hose->first_busno=first_free_busno;
403 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
406 first_free_busno=hose->last_busno+1;
407 printf ("PCI on bus %02x - %02x\n",
408 hose->first_busno,hose->last_busno);
410 printf (" PCI: disabled\n");
414 gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */
419 int board_early_init_r(void)
421 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
422 const u8 flash_esel = 1;
425 * Remap Boot flash + PROMJET region to caching-inhibited
426 * so that flash can be erased properly.
429 /* Flush d-cache and invalidate i-cache of any FLASH data */
433 /* invalidate existing TLB entry for flash + promjet */
434 disable_tlb(flash_esel);
436 set_tlb(1, flashbase, flashbase, /* tlb, epn, rpn */
437 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */
438 0, flash_esel, BOOKE_PAGESZ_256M, 1); /* ts, esel, tsize, iprot */
443 #ifdef CONFIG_GET_CLK_FROM_ICS307
444 /* decode S[0-2] to Output Divider (OD) */
447 10, 2, 8, 4, 5, 7, 3, 6
450 /* Calculate frequency being generated by ICS307-02 clock chip based upon
451 * the control bytes being programmed into it. */
452 /* XXX: This function should probably go into a common library */
454 ics307_clk_freq (unsigned char cw0, unsigned char cw1, unsigned char cw2)
456 const unsigned long long InputFrequency = CONFIG_ICS307_REFCLK_HZ;
457 unsigned long VDW = ((cw1 << 1) & 0x1FE) + ((cw2 >> 7) & 1);
458 unsigned long RDW = cw2 & 0x7F;
459 unsigned long OD = ics307_S_to_OD[cw0 & 0x7];
462 /* CLK1Frequency = InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD) */
464 /* cw0: C1 C0 TTL F1 F0 S2 S1 S0
465 * cw1: V8 V7 V6 V5 V4 V3 V2 V1
466 * cw2: V0 R6 R5 R4 R3 R2 R1 R0
468 * R6:R0 = Reference Divider Word (RDW)
469 * V8:V0 = VCO Divider Word (VDW)
470 * S2:S0 = Output Divider Select (OD)
471 * F1:F0 = Function of CLK2 Output
473 * C1:C0 = internal load capacitance for cyrstal
476 /* Adding 1 to get a "nicely" rounded number, but this needs
477 * more tweaking to get a "properly" rounded number. */
479 freq = 1 + (InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD));
481 debug("ICS307: CW[0-2]: %02X %02X %02X => %u Hz\n", cw0, cw1, cw2,
487 get_board_sys_clk(ulong dummy)
489 return ics307_clk_freq (
490 in8(PIXIS_BASE + PIXIS_VSYSCLK0),
491 in8(PIXIS_BASE + PIXIS_VSYSCLK1),
492 in8(PIXIS_BASE + PIXIS_VSYSCLK2)
497 get_board_ddr_clk(ulong dummy)
499 return ics307_clk_freq (
500 in8(PIXIS_BASE + PIXIS_VDDRCLK0),
501 in8(PIXIS_BASE + PIXIS_VDDRCLK1),
502 in8(PIXIS_BASE + PIXIS_VDDRCLK2)
507 get_board_sys_clk(ulong dummy)
512 i = in8(PIXIS_BASE + PIXIS_SPD);
546 get_board_ddr_clk(ulong dummy)
551 i = in8(PIXIS_BASE + PIXIS_SPD);
585 int is_sata_supported(void)
587 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
589 (gur->pordevsr & MPC85xx_PORDEVSR_SRDS2_IO_SEL) >> 27;
590 if (sdrs2_io_sel & 0x04)
596 int board_eth_init(bd_t *bis)
598 #ifdef CONFIG_TSEC_ENET
599 struct tsec_info_struct tsec_info[2];
600 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
603 (gur->pordevsr & MPC85xx_PORDEVSR_SRDS2_IO_SEL) >> 27;
606 SET_STD_TSEC_INFO(tsec_info[num], 1);
607 if ((sdrs2_io_sel == 4) || (sdrs2_io_sel == 6)) {
608 tsec_info[num].phyaddr = 0;
609 tsec_info[num].flags |= TSEC_SGMII;
614 SET_STD_TSEC_INFO(tsec_info[num], 3);
615 if (sdrs2_io_sel == 4) {
616 tsec_info[num].phyaddr = 1;
617 tsec_info[num].flags |= TSEC_SGMII;
623 printf("No TSECs initialized\n");
627 if ((sdrs2_io_sel == 4) || (sdrs2_io_sel == 6))
628 fsl_sgmii_riser_init(tsec_info, num);
630 tsec_eth_init(bis, tsec_info, num);
632 return pci_eth_init(bis);
635 #if defined(CONFIG_OF_BOARD_SETUP)
636 extern void ft_fsl_pci_setup(void *blob, const char *pci_alias,
637 struct pci_controller *hose);
639 void ft_board_setup(void *blob, bd_t *bd)
641 ft_cpu_setup(blob, bd);
644 ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
647 ft_fsl_pci_setup(blob, "pci1", &pcie2_hose);
650 ft_fsl_pci_setup(blob, "pci2", &pcie1_hose);
653 ft_fsl_pci_setup(blob, "pci3", &pcie3_hose);