2 * Copyright 2008 Freescale Semiconductor.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/processor.h>
28 #include <asm/cache.h>
29 #include <asm/immap_85xx.h>
30 #include <asm/immap_fsl_pci.h>
31 #include <asm/fsl_ddr_sdram.h>
36 #include <spd_sdram.h>
37 #include <fdt_support.h>
41 #include "../common/pixis.h"
42 #include "../common/sgmii_riser.h"
44 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
45 extern void ddr_enable_ecc(unsigned int dram_size);
48 phys_size_t fixed_sdram(void);
52 printf ("Board: MPC8536DS, System ID: 0x%02x, "
53 "System Version: 0x%02x, FPGA Version: 0x%02x\n",
54 in8(PIXIS_BASE + PIXIS_ID), in8(PIXIS_BASE + PIXIS_VER),
55 in8(PIXIS_BASE + PIXIS_PVER));
60 initdram(int board_type)
62 phys_size_t dram_size = 0;
64 puts("Initializing....");
66 #ifdef CONFIG_SPD_EEPROM
67 dram_size = fsl_ddr_sdram();
69 dram_size = setup_ddr_tlbs(dram_size / 0x100000);
71 dram_size *= 0x100000;
73 dram_size = fixed_sdram();
76 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
78 * Initialize and enable DDR ECC.
80 ddr_enable_ecc(dram_size);
86 #if !defined(CONFIG_SPD_EEPROM)
88 * Fixed sdram init -- doesn't use serial presence detect.
91 phys_size_t fixed_sdram (void)
93 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
94 volatile ccsr_ddr_t *ddr= &immap->im_ddr;
97 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
98 ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
100 ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
101 ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
102 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
103 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
104 ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
105 ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
106 ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
107 ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
108 ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
109 ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;
111 #if defined (CONFIG_DDR_ECC)
112 ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN;
113 ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS;
114 ddr->err_sbe = CONFIG_SYS_DDR_SBE;
120 ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
122 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
124 debug("DDR - 1st controller: memory initializing\n");
126 * Poll until memory is initialized.
127 * 512 Meg at 400 might hit this 200 times or so.
129 while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) {
132 debug("DDR: memory initialized\n\n");
137 return 512 * 1024 * 1024;
143 static struct pci_controller pci1_hose;
147 static struct pci_controller pcie1_hose;
151 static struct pci_controller pcie2_hose;
155 static struct pci_controller pcie3_hose;
158 int first_free_busno=0;
163 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
164 uint devdisr = gur->devdisr;
166 (gur->pordevsr & MPC85xx_PORDEVSR_SRDS2_IO_SEL) >> 27;
167 uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
168 uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
170 debug(" pci_init_board: devdisr=%x, sdrs2_io_sel=%x, io_sel=%x,\
171 host_agent=%x\n", devdisr, sdrs2_io_sel, io_sel, host_agent);
173 if (sdrs2_io_sel == 7)
174 printf(" Serdes2 disalbed\n");
175 else if (sdrs2_io_sel == 4) {
176 printf(" eTSEC1 is in sgmii mode.\n");
177 printf(" eTSEC3 is in sgmii mode.\n");
178 } else if (sdrs2_io_sel == 6)
179 printf(" eTSEC1 is in sgmii mode.\n");
183 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE3_ADDR;
184 extern void fsl_pci_init(struct pci_controller *hose);
185 struct pci_controller *hose = &pcie3_hose;
186 int pcie_ep = (host_agent == 1);
187 int pcie_configured = (io_sel == 7);
189 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
190 printf ("\n PCIE3 connected to Slot3 as %s (base address %x)",
191 pcie_ep ? "End Point" : "Root Complex",
193 if (pci->pme_msg_det) {
194 pci->pme_msg_det = 0xffffffff;
195 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
200 pci_set_region(hose->regions + 0,
201 CONFIG_SYS_PCI_MEMORY_BUS,
202 CONFIG_SYS_PCI_MEMORY_PHYS,
203 CONFIG_SYS_PCI_MEMORY_SIZE,
204 PCI_REGION_MEM | PCI_REGION_MEMORY);
206 /* outbound memory */
207 pci_set_region(hose->regions + 1,
208 CONFIG_SYS_PCIE3_MEM_BASE,
209 CONFIG_SYS_PCIE3_MEM_PHYS,
210 CONFIG_SYS_PCIE3_MEM_SIZE,
214 pci_set_region(hose->regions + 2,
215 CONFIG_SYS_PCIE3_IO_BASE,
216 CONFIG_SYS_PCIE3_IO_PHYS,
217 CONFIG_SYS_PCIE3_IO_SIZE,
220 hose->region_count = 3;
222 hose->first_busno=first_free_busno;
223 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
227 first_free_busno=hose->last_busno+1;
228 printf (" PCIE3 on bus %02x - %02x\n",
229 hose->first_busno,hose->last_busno);
231 printf (" PCIE3: disabled\n");
236 gur->devdisr |= MPC85xx_DEVDISR_PCIE3; /* disable */
241 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
242 extern void fsl_pci_init(struct pci_controller *hose);
243 struct pci_controller *hose = &pcie1_hose;
244 int pcie_ep = (host_agent == 5);
245 int pcie_configured = (io_sel == 2 || io_sel == 3
246 || io_sel == 5 || io_sel == 7);
248 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
249 printf ("\n PCIE1 connected to Slot1 as %s (base address %x)",
250 pcie_ep ? "End Point" : "Root Complex",
252 if (pci->pme_msg_det) {
253 pci->pme_msg_det = 0xffffffff;
254 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
259 pci_set_region(hose->regions + 0,
260 CONFIG_SYS_PCI_MEMORY_BUS,
261 CONFIG_SYS_PCI_MEMORY_PHYS,
262 CONFIG_SYS_PCI_MEMORY_SIZE,
263 PCI_REGION_MEM | PCI_REGION_MEMORY);
265 /* outbound memory */
266 pci_set_region(hose->regions + 1,
267 CONFIG_SYS_PCIE1_MEM_BASE,
268 CONFIG_SYS_PCIE1_MEM_PHYS,
269 CONFIG_SYS_PCIE1_MEM_SIZE,
273 pci_set_region(hose->regions + 2,
274 CONFIG_SYS_PCIE1_IO_BASE,
275 CONFIG_SYS_PCIE1_IO_PHYS,
276 CONFIG_SYS_PCIE1_IO_SIZE,
279 hose->region_count = 3;
280 #ifdef CONFIG_SYS_PCIE1_MEM_BASE2
281 /* outbound memory */
282 pci_set_region(hose->regions + 3,
283 CONFIG_SYS_PCIE1_MEM_BASE2,
284 CONFIG_SYS_PCIE1_MEM_PHYS2,
285 CONFIG_SYS_PCIE1_MEM_SIZE2,
287 hose->region_count++;
289 hose->first_busno=first_free_busno;
291 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
295 first_free_busno=hose->last_busno+1;
296 printf(" PCIE1 on bus %02x - %02x\n",
297 hose->first_busno,hose->last_busno);
300 printf (" PCIE1: disabled\n");
305 gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
310 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR;
311 extern void fsl_pci_init(struct pci_controller *hose);
312 struct pci_controller *hose = &pcie2_hose;
313 int pcie_ep = (host_agent == 3);
314 int pcie_configured = (io_sel == 5 || io_sel == 7);
316 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
317 printf ("\n PCIE2 connected to Slot 2 as %s (base address %x)",
318 pcie_ep ? "End Point" : "Root Complex",
320 if (pci->pme_msg_det) {
321 pci->pme_msg_det = 0xffffffff;
322 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
327 pci_set_region(hose->regions + 0,
328 CONFIG_SYS_PCI_MEMORY_BUS,
329 CONFIG_SYS_PCI_MEMORY_PHYS,
330 CONFIG_SYS_PCI_MEMORY_SIZE,
331 PCI_REGION_MEM | PCI_REGION_MEMORY);
333 /* outbound memory */
334 pci_set_region(hose->regions + 1,
335 CONFIG_SYS_PCIE2_MEM_BASE,
336 CONFIG_SYS_PCIE2_MEM_PHYS,
337 CONFIG_SYS_PCIE2_MEM_SIZE,
341 pci_set_region(hose->regions + 2,
342 CONFIG_SYS_PCIE2_IO_BASE,
343 CONFIG_SYS_PCIE2_IO_PHYS,
344 CONFIG_SYS_PCIE2_IO_SIZE,
347 hose->region_count = 3;
348 #ifdef CONFIG_SYS_PCIE2_MEM_BASE2
349 /* outbound memory */
350 pci_set_region(hose->regions + 3,
351 CONFIG_SYS_PCIE2_MEM_BASE2,
352 CONFIG_SYS_PCIE2_MEM_PHYS2,
353 CONFIG_SYS_PCIE2_MEM_SIZE2,
355 hose->region_count++;
357 hose->first_busno=first_free_busno;
358 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
361 first_free_busno=hose->last_busno+1;
362 printf (" PCIE2 on bus %02x - %02x\n",
363 hose->first_busno,hose->last_busno);
366 printf (" PCIE2: disabled\n");
371 gur->devdisr |= MPC85xx_DEVDISR_PCIE2; /* disable */
377 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR;
378 extern void fsl_pci_init(struct pci_controller *hose);
379 struct pci_controller *hose = &pci1_hose;
381 uint pci_agent = (host_agent == 6);
382 uint pci_speed = 66666000; /*get_clock_freq (); PCI PSPEED in [4:5] */
384 uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */
385 uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */
388 if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
389 printf ("\n PCI: %d bit, %s MHz, %s, %s, %s (base address %x)\n",
391 (pci_speed == 33333000) ? "33" :
392 (pci_speed == 66666000) ? "66" : "unknown",
393 pci_clk_sel ? "sync" : "async",
394 pci_agent ? "agent" : "host",
395 pci_arb ? "arbiter" : "external-arbiter",
400 pci_set_region(hose->regions + 0,
401 CONFIG_SYS_PCI_MEMORY_BUS,
402 CONFIG_SYS_PCI_MEMORY_PHYS,
403 CONFIG_SYS_PCI_MEMORY_SIZE,
404 PCI_REGION_MEM | PCI_REGION_MEMORY);
406 /* outbound memory */
407 pci_set_region(hose->regions + 1,
408 CONFIG_SYS_PCI1_MEM_BASE,
409 CONFIG_SYS_PCI1_MEM_PHYS,
410 CONFIG_SYS_PCI1_MEM_SIZE,
414 pci_set_region(hose->regions + 2,
415 CONFIG_SYS_PCI1_IO_BASE,
416 CONFIG_SYS_PCI1_IO_PHYS,
417 CONFIG_SYS_PCI1_IO_SIZE,
419 hose->region_count = 3;
420 #ifdef CONFIG_SYS_PCI1_MEM_BASE2
421 /* outbound memory */
422 pci_set_region(hose->regions + 3,
423 CONFIG_SYS_PCI1_MEM_BASE2,
424 CONFIG_SYS_PCI1_MEM_PHYS2,
425 CONFIG_SYS_PCI1_MEM_SIZE2,
427 hose->region_count++;
429 hose->first_busno=first_free_busno;
430 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
433 first_free_busno=hose->last_busno+1;
434 printf ("PCI on bus %02x - %02x\n",
435 hose->first_busno,hose->last_busno);
437 printf (" PCI: disabled\n");
441 gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */
446 int board_early_init_r(void)
448 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
449 const u8 flash_esel = 1;
452 * Remap Boot flash + PROMJET region to caching-inhibited
453 * so that flash can be erased properly.
456 /* Flush d-cache and invalidate i-cache of any FLASH data */
460 /* invalidate existing TLB entry for flash + promjet */
461 disable_tlb(flash_esel);
463 set_tlb(1, flashbase, flashbase, /* tlb, epn, rpn */
464 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */
465 0, flash_esel, BOOKE_PAGESZ_256M, 1); /* ts, esel, tsize, iprot */
470 #ifdef CONFIG_GET_CLK_FROM_ICS307
471 /* decode S[0-2] to Output Divider (OD) */
474 10, 2, 8, 4, 5, 7, 3, 6
477 /* Calculate frequency being generated by ICS307-02 clock chip based upon
478 * the control bytes being programmed into it. */
479 /* XXX: This function should probably go into a common library */
481 ics307_clk_freq (unsigned char cw0, unsigned char cw1, unsigned char cw2)
483 const unsigned long long InputFrequency = CONFIG_ICS307_REFCLK_HZ;
484 unsigned long VDW = ((cw1 << 1) & 0x1FE) + ((cw2 >> 7) & 1);
485 unsigned long RDW = cw2 & 0x7F;
486 unsigned long OD = ics307_S_to_OD[cw0 & 0x7];
489 /* CLK1Frequency = InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD) */
491 /* cw0: C1 C0 TTL F1 F0 S2 S1 S0
492 * cw1: V8 V7 V6 V5 V4 V3 V2 V1
493 * cw2: V0 R6 R5 R4 R3 R2 R1 R0
495 * R6:R0 = Reference Divider Word (RDW)
496 * V8:V0 = VCO Divider Word (VDW)
497 * S2:S0 = Output Divider Select (OD)
498 * F1:F0 = Function of CLK2 Output
500 * C1:C0 = internal load capacitance for cyrstal
503 /* Adding 1 to get a "nicely" rounded number, but this needs
504 * more tweaking to get a "properly" rounded number. */
506 freq = 1 + (InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD));
508 debug("ICS307: CW[0-2]: %02X %02X %02X => %u Hz\n", cw0, cw1, cw2,
514 get_board_sys_clk(ulong dummy)
516 return ics307_clk_freq (
517 in8(PIXIS_BASE + PIXIS_VSYSCLK0),
518 in8(PIXIS_BASE + PIXIS_VSYSCLK1),
519 in8(PIXIS_BASE + PIXIS_VSYSCLK2)
524 get_board_ddr_clk(ulong dummy)
526 return ics307_clk_freq (
527 in8(PIXIS_BASE + PIXIS_VDDRCLK0),
528 in8(PIXIS_BASE + PIXIS_VDDRCLK1),
529 in8(PIXIS_BASE + PIXIS_VDDRCLK2)
534 get_board_sys_clk(ulong dummy)
539 i = in8(PIXIS_BASE + PIXIS_SPD);
573 get_board_ddr_clk(ulong dummy)
578 i = in8(PIXIS_BASE + PIXIS_SPD);
612 int is_sata_supported(void)
614 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
615 uint devdisr = gur->devdisr;
617 (gur->pordevsr & MPC85xx_PORDEVSR_SRDS2_IO_SEL) >> 27;
618 if (sdrs2_io_sel & 0x04)
624 int board_eth_init(bd_t *bis)
626 #ifdef CONFIG_TSEC_ENET
627 struct tsec_info_struct tsec_info[2];
628 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
631 (gur->pordevsr & MPC85xx_PORDEVSR_SRDS2_IO_SEL) >> 27;
634 SET_STD_TSEC_INFO(tsec_info[num], 1);
635 if ((sdrs2_io_sel == 4) || (sdrs2_io_sel == 6)) {
636 tsec_info[num].phyaddr = 0;
637 tsec_info[num].flags |= TSEC_SGMII;
642 SET_STD_TSEC_INFO(tsec_info[num], 3);
643 if (sdrs2_io_sel == 4) {
644 tsec_info[num].phyaddr = 1;
645 tsec_info[num].flags |= TSEC_SGMII;
651 printf("No TSECs initialized\n");
655 if ((sdrs2_io_sel == 4) || (sdrs2_io_sel == 6))
656 fsl_sgmii_riser_init(tsec_info, num);
658 tsec_eth_init(bis, tsec_info, num);
660 return pci_eth_init(bis);
663 #if defined(CONFIG_OF_BOARD_SETUP)
665 ft_board_setup(void *blob, bd_t *bd)
670 ft_cpu_setup(blob, bd);
672 node = fdt_path_offset(blob, "/aliases");
676 path = fdt_getprop(blob, node, "pci0", NULL);
678 tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno;
679 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
683 path = fdt_getprop(blob, node, "pci1", NULL);
685 tmp[1] = pcie2_hose.last_busno - pcie2_hose.first_busno;
686 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
690 path = fdt_getprop(blob, node, "pci2", NULL);
692 tmp[1] = pcie1_hose.last_busno - pcie1_hose.first_busno;
693 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
697 path = fdt_getprop(blob, node, "pci3", NULL);
699 tmp[1] = pcie3_hose.last_busno - pcie3_hose.first_busno;
700 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);