2 * Copyright 2004 Freescale Semiconductor.
3 * (C) Copyright 2002,2003, Motorola Inc.
4 * Xianghua Xiao, (X.Xiao@motorola.com)
6 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 #include <asm/processor.h>
31 #include <asm/immap_85xx.h>
34 #include <fdt_support.h>
36 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
37 extern void ddr_enable_ecc(unsigned int dram_size);
40 extern long int spd_sdram(void);
42 void local_bus_init(void);
43 void sdram_init(void);
44 long int fixed_sdram(void);
47 int board_early_init_f (void)
57 printf(" PCI1: 32 bit, %d MHz (compiled)\n",
58 CONFIG_SYS_CLK_FREQ / 1000000);
60 printf(" PCI1: disabled\n");
64 * Initialize local bus.
73 initdram(int board_type)
76 extern long spd_sdram (void);
78 puts("Initializing\n");
80 #if defined(CONFIG_DDR_DLL)
82 volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
86 * Work around to stabilize DDR DLL
88 temp_ddrdll = gur->ddrdllcr;
89 gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000;
90 asm("sync;isync;msync");
94 #if defined(CONFIG_SPD_EEPROM)
95 dram_size = spd_sdram ();
97 dram_size = fixed_sdram ();
100 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
102 * Initialize and enable DDR ECC.
104 ddr_enable_ecc(dram_size);
118 * Initialize Local Bus
124 volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
125 volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
133 * Fix Local Bus clock glitch when DLL is enabled.
135 * If localbus freq is < 66Mhz, DLL bypass mode must be used.
136 * If localbus freq is > 133Mhz, DLL can be safely enabled.
137 * Between 66 and 133, the DLL is enabled with an override workaround.
140 get_sys_info(&sysinfo);
141 clkdiv = lbc->lcrr & 0x0f;
142 lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
145 lbc->lcrr = CFG_LBC_LCRR | 0x80000000; /* DLL Bypass */
147 } else if (lbc_hz >= 133) {
148 lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */
152 * On REV1 boards, need to change CLKDIV before enable DLL.
153 * Default CLKDIV is 8, change it to 4 temporarily.
155 uint pvr = get_pvr();
156 uint temp_lbcdll = 0;
158 if (pvr == PVR_85xx_REV1) {
159 /* FIXME: Justify the high bit here. */
160 lbc->lcrr = 0x10000004;
163 lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */
167 * Sample LBC DLL ctrl reg, upshift it to set the
170 temp_lbcdll = gur->lbcdllcr;
171 gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
172 asm("sync;isync;msync");
178 * Initialize SDRAM memory on the Local Bus.
184 volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
185 uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
188 print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
191 * Setup SDRAM Base and Option Registers
193 lbc->or2 = CFG_OR2_PRELIM;
194 lbc->br2 = CFG_BR2_PRELIM;
195 lbc->lbcr = CFG_LBC_LBCR;
198 lbc->lsrt = CFG_LBC_LSRT;
199 lbc->mrtpr = CFG_LBC_MRTPR;
203 * Configure the SDRAM controller.
205 lbc->lsdmr = CFG_LBC_LSDMR_1;
208 ppcDcbf((unsigned long) sdram_addr);
211 lbc->lsdmr = CFG_LBC_LSDMR_2;
214 ppcDcbf((unsigned long) sdram_addr);
217 lbc->lsdmr = CFG_LBC_LSDMR_3;
220 ppcDcbf((unsigned long) sdram_addr);
223 lbc->lsdmr = CFG_LBC_LSDMR_4;
226 ppcDcbf((unsigned long) sdram_addr);
229 lbc->lsdmr = CFG_LBC_LSDMR_5;
232 ppcDcbf((unsigned long) sdram_addr);
237 #if defined(CFG_DRAM_TEST)
240 uint *pstart = (uint *) CFG_MEMTEST_START;
241 uint *pend = (uint *) CFG_MEMTEST_END;
244 printf("SDRAM test phase 1:\n");
245 for (p = pstart; p < pend; p++)
248 for (p = pstart; p < pend; p++) {
249 if (*p != 0xaaaaaaaa) {
250 printf ("SDRAM test fails at: %08x\n", (uint) p);
255 printf("SDRAM test phase 2:\n");
256 for (p = pstart; p < pend; p++)
259 for (p = pstart; p < pend; p++) {
260 if (*p != 0x55555555) {
261 printf ("SDRAM test fails at: %08x\n", (uint) p);
266 printf("SDRAM test passed.\n");
272 #if !defined(CONFIG_SPD_EEPROM)
273 /*************************************************************************
274 * fixed sdram init -- doesn't use serial presence detect.
275 ************************************************************************/
276 long int fixed_sdram (void)
279 volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR);
281 ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
282 ddr->cs0_config = CFG_DDR_CS0_CONFIG;
283 ddr->timing_cfg_1 = CFG_DDR_TIMING_1;
284 ddr->timing_cfg_2 = CFG_DDR_TIMING_2;
285 ddr->sdram_mode = CFG_DDR_MODE;
286 ddr->sdram_interval = CFG_DDR_INTERVAL;
287 #if defined (CONFIG_DDR_ECC)
288 ddr->err_disable = 0x0000000D;
289 ddr->err_sbe = 0x00ff0000;
291 asm("sync;isync;msync");
293 #if defined (CONFIG_DDR_ECC)
294 /* Enable ECC checking */
295 ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000);
297 ddr->sdram_cfg = CFG_DDR_CONTROL;
299 asm("sync; isync; msync");
302 return CFG_SDRAM_SIZE * 1024 * 1024;
304 #endif /* !defined(CONFIG_SPD_EEPROM) */
307 #if defined(CONFIG_PCI)
309 * Initialize PCI Devices, report devices found.
313 static struct pci_controller hose;
315 #endif /* CONFIG_PCI */
322 pci_mpc85xx_init(&hose);
323 #endif /* CONFIG_PCI */
327 #if defined(CONFIG_OF_BOARD_SETUP)
329 ft_board_setup(void *blob, bd_t *bd)
334 ft_cpu_setup(blob, bd);
336 node = fdt_path_offset(blob, "/aliases");
340 path = fdt_getprop(blob, node, "pci0", NULL);
342 tmp[1] = hose.last_busno - hose.first_busno;
343 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);