2 * Copyright 2004 Freescale Semiconductor.
3 * (C) Copyright 2002,2003, Motorola Inc.
4 * Xianghua Xiao, (X.Xiao@motorola.com)
6 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 #include <asm/processor.h>
31 #include <asm/immap_85xx.h>
32 #include <spd_sdram.h>
34 #include <fdt_support.h>
36 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
37 extern void ddr_enable_ecc(unsigned int dram_size);
40 void local_bus_init(void);
41 void sdram_init(void);
42 long int fixed_sdram(void);
49 printf(" PCI1: 32 bit, %d MHz (compiled)\n",
50 CONFIG_SYS_CLK_FREQ / 1000000);
52 printf(" PCI1: disabled\n");
56 * Initialize local bus.
65 initdram(int board_type)
69 puts("Initializing\n");
71 #if defined(CONFIG_DDR_DLL)
73 volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
77 * Work around to stabilize DDR DLL
79 temp_ddrdll = gur->ddrdllcr;
80 gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000;
81 asm("sync;isync;msync");
85 #if defined(CONFIG_SPD_EEPROM)
86 dram_size = spd_sdram ();
88 dram_size = fixed_sdram ();
91 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
93 * Initialize and enable DDR ECC.
95 ddr_enable_ecc(dram_size);
109 * Initialize Local Bus
115 volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
116 volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
124 * Fix Local Bus clock glitch when DLL is enabled.
126 * If localbus freq is < 66Mhz, DLL bypass mode must be used.
127 * If localbus freq is > 133Mhz, DLL can be safely enabled.
128 * Between 66 and 133, the DLL is enabled with an override workaround.
131 get_sys_info(&sysinfo);
132 clkdiv = lbc->lcrr & 0x0f;
133 lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
136 lbc->lcrr = CFG_LBC_LCRR | 0x80000000; /* DLL Bypass */
138 } else if (lbc_hz >= 133) {
139 lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */
143 * On REV1 boards, need to change CLKDIV before enable DLL.
144 * Default CLKDIV is 8, change it to 4 temporarily.
146 uint pvr = get_pvr();
147 uint temp_lbcdll = 0;
149 if (pvr == PVR_85xx_REV1) {
150 /* FIXME: Justify the high bit here. */
151 lbc->lcrr = 0x10000004;
154 lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */
158 * Sample LBC DLL ctrl reg, upshift it to set the
161 temp_lbcdll = gur->lbcdllcr;
162 gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
163 asm("sync;isync;msync");
169 * Initialize SDRAM memory on the Local Bus.
175 volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
176 uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
179 print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
182 * Setup SDRAM Base and Option Registers
184 lbc->or2 = CFG_OR2_PRELIM;
185 lbc->br2 = CFG_BR2_PRELIM;
186 lbc->lbcr = CFG_LBC_LBCR;
189 lbc->lsrt = CFG_LBC_LSRT;
190 lbc->mrtpr = CFG_LBC_MRTPR;
194 * Configure the SDRAM controller.
196 lbc->lsdmr = CFG_LBC_LSDMR_1;
199 ppcDcbf((unsigned long) sdram_addr);
202 lbc->lsdmr = CFG_LBC_LSDMR_2;
205 ppcDcbf((unsigned long) sdram_addr);
208 lbc->lsdmr = CFG_LBC_LSDMR_3;
211 ppcDcbf((unsigned long) sdram_addr);
214 lbc->lsdmr = CFG_LBC_LSDMR_4;
217 ppcDcbf((unsigned long) sdram_addr);
220 lbc->lsdmr = CFG_LBC_LSDMR_5;
223 ppcDcbf((unsigned long) sdram_addr);
227 #if !defined(CONFIG_SPD_EEPROM)
228 /*************************************************************************
229 * fixed sdram init -- doesn't use serial presence detect.
230 ************************************************************************/
231 long int fixed_sdram (void)
234 volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR);
236 ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
237 ddr->cs0_config = CFG_DDR_CS0_CONFIG;
238 ddr->timing_cfg_1 = CFG_DDR_TIMING_1;
239 ddr->timing_cfg_2 = CFG_DDR_TIMING_2;
240 ddr->sdram_mode = CFG_DDR_MODE;
241 ddr->sdram_interval = CFG_DDR_INTERVAL;
242 #if defined (CONFIG_DDR_ECC)
243 ddr->err_disable = 0x0000000D;
244 ddr->err_sbe = 0x00ff0000;
246 asm("sync;isync;msync");
248 #if defined (CONFIG_DDR_ECC)
249 /* Enable ECC checking */
250 ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000);
252 ddr->sdram_cfg = CFG_DDR_CONTROL;
254 asm("sync; isync; msync");
257 return CFG_SDRAM_SIZE * 1024 * 1024;
259 #endif /* !defined(CONFIG_SPD_EEPROM) */
262 #if defined(CONFIG_PCI)
264 * Initialize PCI Devices, report devices found.
268 static struct pci_controller hose;
270 #endif /* CONFIG_PCI */
277 pci_mpc85xx_init(&hose);
278 #endif /* CONFIG_PCI */
282 #if defined(CONFIG_OF_BOARD_SETUP)
284 ft_board_setup(void *blob, bd_t *bd)
289 ft_cpu_setup(blob, bd);
291 node = fdt_path_offset(blob, "/aliases");
295 path = fdt_getprop(blob, node, "pci0", NULL);
297 tmp[1] = hose.last_busno - hose.first_busno;
298 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);