2 * Copyright 2004 Freescale Semiconductor.
3 * (C) Copyright 2002,2003, Motorola Inc.
4 * Xianghua Xiao, (X.Xiao@motorola.com)
6 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 #include <asm/processor.h>
32 #include <asm/immap_85xx.h>
33 #include <asm/fsl_ddr_sdram.h>
35 #include <fdt_support.h>
37 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
38 extern void ddr_enable_ecc(unsigned int dram_size);
41 void local_bus_init(void);
48 printf("PCI1: 32 bit, %d MHz (compiled)\n",
49 CONFIG_SYS_CLK_FREQ / 1000000);
51 printf("PCI1: disabled\n");
55 * Initialize local bus.
63 * Initialize Local Bus
69 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
70 volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
78 * Fix Local Bus clock glitch when DLL is enabled.
80 * If localbus freq is < 66MHz, DLL bypass mode must be used.
81 * If localbus freq is > 133MHz, DLL can be safely enabled.
82 * Between 66 and 133, the DLL is enabled with an override workaround.
85 get_sys_info(&sysinfo);
86 clkdiv = lbc->lcrr & LCRR_CLKDIV;
87 lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
90 lbc->lcrr = CONFIG_SYS_LBC_LCRR | LCRR_DBYP; /* DLL Bypass */
92 } else if (lbc_hz >= 133) {
93 lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~LCRR_DBYP); /* DLL Enabled */
97 * On REV1 boards, need to change CLKDIV before enable DLL.
98 * Default CLKDIV is 8, change it to 4 temporarily.
100 uint pvr = get_pvr();
101 uint temp_lbcdll = 0;
103 if (pvr == PVR_85xx_REV1) {
104 /* FIXME: Justify the high bit here. */
105 lbc->lcrr = 0x10000004;
108 lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~LCRR_DBYP); /* DLL Enabled */
112 * Sample LBC DLL ctrl reg, upshift it to set the
115 temp_lbcdll = gur->lbcdllcr;
116 gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
117 asm("sync;isync;msync");
123 * Initialize SDRAM memory on the Local Bus.
125 void lbc_sdram_init(void)
127 volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
128 uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
131 print_size(CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024,
135 * Setup SDRAM Base and Option Registers
137 set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
138 set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
139 lbc->lbcr = CONFIG_SYS_LBC_LBCR;
142 lbc->lsrt = CONFIG_SYS_LBC_LSRT;
143 lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
147 * Configure the SDRAM controller.
149 lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1;
152 ppcDcbf((unsigned long) sdram_addr);
155 lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2;
158 ppcDcbf((unsigned long) sdram_addr);
161 lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_3;
164 ppcDcbf((unsigned long) sdram_addr);
167 lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4;
170 ppcDcbf((unsigned long) sdram_addr);
173 lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5;
176 ppcDcbf((unsigned long) sdram_addr);
180 #if !defined(CONFIG_SPD_EEPROM)
181 /*************************************************************************
182 * fixed sdram init -- doesn't use serial presence detect.
183 ************************************************************************/
184 phys_size_t fixed_sdram(void)
186 #ifndef CONFIG_SYS_RAMBOOT
187 volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC8xxx_DDR_ADDR);
189 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
190 ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
191 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
192 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
193 ddr->sdram_mode = CONFIG_SYS_DDR_MODE;
194 ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
195 #if defined (CONFIG_DDR_ECC)
196 ddr->err_disable = 0x0000000D;
197 ddr->err_sbe = 0x00ff0000;
199 asm("sync;isync;msync");
201 #if defined (CONFIG_DDR_ECC)
202 /* Enable ECC checking */
203 ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL | 0x20000000);
205 ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
207 asm("sync; isync; msync");
210 return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
212 #endif /* !defined(CONFIG_SPD_EEPROM) */
215 #if defined(CONFIG_PCI)
217 * Initialize PCI Devices, report devices found.
221 static struct pci_controller hose;
223 #endif /* CONFIG_PCI */
230 pci_mpc85xx_init(&hose);
231 #endif /* CONFIG_PCI */
235 #if defined(CONFIG_OF_BOARD_SETUP)
237 ft_board_setup(void *blob, bd_t *bd)
242 ft_cpu_setup(blob, bd);
244 node = fdt_path_offset(blob, "/aliases");
248 path = fdt_getprop(blob, node, "pci0", NULL);
250 tmp[1] = hose.last_busno - hose.first_busno;
251 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);