2 * Copyright 2007 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 #include <ppc_asm.tmpl>
25 #include <asm/cache.h>
31 * TLB0 and TLB1 Entries
33 * Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR.
34 * However, CCSRBAR is then relocated to CFG_CCSRBAR right after
35 * these TLB entries are established.
37 * The TLB entries for DDR are dynamically setup in spd_sdram()
38 * and use TLB1 Entries 8 through 15 as needed according to the
41 * MAS0: tlbsel, esel, nv
42 * MAS1: valid, iprot, tid, ts, tsize
43 * MAS2: epn, x0, x1, w, i, m, g, e
44 * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr
57 .section .bootpg, "ax"
63 * Number of TLB0 and TLB1 entries in the following table
68 * TLB0 4K Non-cacheable, guarded
69 * 0xff700000 4K Initial CCSRBAR mapping
71 * This ends up at a TLB0 Index==0 entry, and must not collide
72 * with other TLB0 Entries.
74 .long FSL_BOOKE_MAS0(0, 0, 0)
75 .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
76 .long FSL_BOOKE_MAS2(CFG_CCSRBAR_DEFAULT, (MAS2_I|MAS2_G))
77 .long FSL_BOOKE_MAS3(CFG_CCSRBAR_DEFAULT, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
80 * TLB0 16K Cacheable, guarded
81 * Temporary Global data for initialization
83 * Use four 4K TLB0 entries. These entries must be cacheable
84 * as they provide the bootstrap memory before the memory
85 * controler and real memory have been configured.
87 * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c,
88 * and must not collide with other TLB0 entries.
90 .long FSL_BOOKE_MAS0(0, 0, 0)
91 .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
92 .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR, (MAS2_G))
93 .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
95 .long FSL_BOOKE_MAS0(0, 0, 0)
96 .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
97 .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 4 * 1024, (MAS2_G))
98 .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 4 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
100 .long FSL_BOOKE_MAS0(0, 0, 0)
101 .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
102 .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 8 * 1024, (MAS2_G))
103 .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 8 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
105 .long FSL_BOOKE_MAS0(0, 0, 0)
106 .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
107 .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 12 * 1024, (MAS2_G))
108 .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 12 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
112 * TLB 0: 64M Non-cacheable, guarded
113 * 0xfc000000 64M Covers FLASH at 0xFE800000 and 0xFF800000
114 * Out of reset this entry is only 4K.
116 .long FSL_BOOKE_MAS0(1, 0, 0)
117 .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
118 .long FSL_BOOKE_MAS2(CFG_BOOT_BLOCK, (MAS2_I|MAS2_G))
119 .long FSL_BOOKE_MAS3(CFG_BOOT_BLOCK, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
122 * TLB 1: 1G Non-cacheable, guarded
123 * 0x80000000 1G PCIE 8,9,a,b
125 .long FSL_BOOKE_MAS0(1, 1, 0)
126 .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1G)
127 .long FSL_BOOKE_MAS2(CFG_PCIE_PHYS, (MAS2_I|MAS2_G))
128 .long FSL_BOOKE_MAS3(CFG_PCIE_PHYS, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
131 * TLB 2: 256M Non-cacheable, guarded
133 .long FSL_BOOKE_MAS0(1, 2, 0)
134 .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
135 .long FSL_BOOKE_MAS2(CFG_PCI_PHYS, (MAS2_I|MAS2_G))
136 .long FSL_BOOKE_MAS3(CFG_PCI_PHYS, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
139 * TLB 3: 256M Non-cacheable, guarded
141 .long FSL_BOOKE_MAS0(1, 3, 0)
142 .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
143 .long FSL_BOOKE_MAS2(CFG_PCI_PHYS + 0x10000000, (MAS2_I|MAS2_G))
144 .long FSL_BOOKE_MAS3(CFG_PCI_PHYS + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
147 * TLB 4: 64M Non-cacheable, guarded
148 * 0xe000_0000 1M CCSRBAR
149 * 0xe100_0000 255M PCI IO range
151 .long FSL_BOOKE_MAS0(1, 4, 0)
152 .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
153 .long FSL_BOOKE_MAS2(CFG_CCSRBAR, (MAS2_I|MAS2_G))
154 .long FSL_BOOKE_MAS3(CFG_CCSRBAR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
156 #ifdef CFG_LBC_CACHE_BASE
158 * TLB 5: 64M Cacheable, non-guarded
160 .long FSL_BOOKE_MAS0(1, 5, 0)
161 .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
162 .long FSL_BOOKE_MAS2(CFG_LBC_CACHE_BASE, 0)
163 .long FSL_BOOKE_MAS3(CFG_LBC_CACHE_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
166 * TLB 6: 64M Non-cacheable, guarded
167 * 0xf8000000 64M PIXIS 0xF8000000 - 0xFBFFFFFF
169 .long FSL_BOOKE_MAS0(1, 6, 0)
170 .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
171 .long FSL_BOOKE_MAS2(CFG_LBC_NONCACHE_BASE, (MAS2_I|MAS2_G))
172 .long FSL_BOOKE_MAS3(CFG_LBC_NONCACHE_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))