2 * Copyright 2007,2009-2010 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/processor.h>
28 #include <asm/immap_85xx.h>
29 #include <asm/fsl_pci.h>
30 #include <asm/fsl_ddr_sdram.h>
34 #include <fdt_support.h>
38 #include "../common/sgmii_riser.h"
42 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
43 volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
44 volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
46 u8 *pixis_base = (u8 *)PIXIS_BASE;
48 if ((uint)&gur->porpllsr != 0xe00e0000) {
49 printf("immap size error %lx\n",(ulong)&gur->porpllsr);
51 printf ("Board: MPC8544DS, Sys ID: 0x%02x, "
52 "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
53 in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
54 in_8(pixis_base + PIXIS_PVER));
56 vboot = in_8(pixis_base + PIXIS_VBOOT);
57 if (vboot & PIXIS_VBOOT_FMAP)
58 printf ("vBank: %d\n", ((vboot & PIXIS_VBOOT_FBANK) >> 6));
62 lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */
63 lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */
64 ecm->eedr = 0xffffffff; /* Clear ecm errors */
65 ecm->eeer = 0xffffffff; /* Enable ecm errors */
71 initdram(int board_type)
75 puts("Initializing\n");
77 dram_size = fsl_ddr_sdram();
79 dram_size = setup_ddr_tlbs(dram_size / 0x100000);
81 dram_size *= 0x100000;
88 static struct pci_controller pci1_hose;
92 static struct pci_controller pcie1_hose;
96 static struct pci_controller pcie2_hose;
100 static struct pci_controller pcie3_hose;
103 void pci_init_board(void)
105 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
106 struct fsl_pci_info pci_info[4];
107 u32 devdisr, pordevsr, io_sel;
108 u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel;
109 int first_free_busno = 0;
112 int pcie_ep, pcie_configured;
114 devdisr = in_be32(&gur->devdisr);
115 pordevsr = in_be32(&gur->pordevsr);
116 porpllsr = in_be32(&gur->porpllsr);
117 io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
119 debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel);
122 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS))
123 printf("eTSEC1 is in sgmii mode.\n");
124 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
125 printf("eTSEC3 is in sgmii mode.\n");
130 pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_3, io_sel);
132 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)){
133 SET_STD_PCIE_INFO(pci_info[num], 3);
134 pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info[num].regs);
135 #ifdef CONFIG_SYS_PCIE3_MEM_BUS2
136 /* outbound memory */
137 pci_set_region(&pcie3_hose.regions[0],
138 CONFIG_SYS_PCIE3_MEM_BUS2,
139 CONFIG_SYS_PCIE3_MEM_PHYS2,
140 CONFIG_SYS_PCIE3_MEM_SIZE2,
143 pcie3_hose.region_count = 1;
145 printf("PCIE3: connected to ULI as %s (base addr %lx)\n",
146 pcie_ep ? "Endpoint" : "Root Complex",
148 first_free_busno = fsl_pci_init_port(&pci_info[num++],
149 &pcie3_hose, first_free_busno);
152 * Activate ULI1575 legacy chip by performing a fake
153 * memory access. Needed to make ULI RTC work.
155 in_be32((u32 *)CONFIG_SYS_PCIE3_MEM_BUS);
157 printf("PCIE3: disabled\n");
161 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE3); /* disable */
165 pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
167 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
168 SET_STD_PCIE_INFO(pci_info[num], 1);
169 pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
170 #ifdef CONFIG_SYS_PCIE1_MEM_BUS2
171 /* outbound memory */
172 pci_set_region(&pcie1_hose.regions[0],
173 CONFIG_SYS_PCIE1_MEM_BUS2,
174 CONFIG_SYS_PCIE1_MEM_PHYS2,
175 CONFIG_SYS_PCIE1_MEM_SIZE2,
178 pcie1_hose.region_count = 1;
180 printf("PCIE1: connected to Slot 2 as %s (base addr %lx)\n",
181 pcie_ep ? "Endpoint" : "Root Complex",
184 first_free_busno = fsl_pci_init_port(&pci_info[num++],
185 &pcie1_hose, first_free_busno);
187 printf("PCIE1: disabled\n");
192 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */
196 pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel);
198 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)){
199 SET_STD_PCIE_INFO(pci_info[num], 2);
200 pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
201 #ifdef CONFIG_SYS_PCIE2_MEM_BUS2
202 /* outbound memory */
203 pci_set_region(&pcie2_hose.regions[0],
204 CONFIG_SYS_PCIE2_MEM_BUS2,
205 CONFIG_SYS_PCIE2_MEM_PHYS2,
206 CONFIG_SYS_PCIE2_MEM_SIZE2,
209 pcie2_hose.region_count = 1;
211 printf("PCIE2: connected to Slot 1 as %s (base addr %lx)\n",
212 pcie_ep ? "Endpoint" : "Root Complex",
214 first_free_busno = fsl_pci_init_port(&pci_info[num++],
215 &pcie2_hose, first_free_busno);
217 printf("PCIE2: disabled\n");
222 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE2); /* disable */
226 pci_speed = 66666000;
228 pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
229 pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
231 if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
232 SET_STD_PCI_INFO(pci_info[num], 1);
233 pci_agent = fsl_setup_hose(&pci1_hose, pci_info[num].regs);
234 printf("PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
236 (pci_speed == 33333000) ? "33" :
237 (pci_speed == 66666000) ? "66" : "unknown",
238 pci_clk_sel ? "sync" : "async",
239 pci_agent ? "agent" : "host",
240 pci_arb ? "arbiter" : "external-arbiter",
243 first_free_busno = fsl_pci_init_port(&pci_info[num++],
244 &pci1_hose, first_free_busno);
246 printf("PCI: disabled\n");
251 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */
256 int last_stage_init(void)
263 get_board_sys_clk(ulong dummy)
265 u8 i, go_bit, rd_clks;
267 u8 *pixis_base = (u8 *)PIXIS_BASE;
269 go_bit = in_8(pixis_base + PIXIS_VCTL);
272 rd_clks = in_8(pixis_base + PIXIS_VCFGEN0);
276 * Only if both go bit and the SCLK bit in VCFGEN0 are set
277 * should we be using the AUX register. Remember, we also set the
278 * GO bit to boot from the alternate bank on the on-board flash
283 i = in_8(pixis_base + PIXIS_AUX);
285 i = in_8(pixis_base + PIXIS_SPD);
287 i = in_8(pixis_base + PIXIS_SPD);
322 int board_eth_init(bd_t *bis)
324 #ifdef CONFIG_TSEC_ENET
325 struct tsec_info_struct tsec_info[2];
326 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
327 uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
331 SET_STD_TSEC_INFO(tsec_info[num], 1);
332 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS))
333 tsec_info[num].flags |= TSEC_SGMII;
337 SET_STD_TSEC_INFO(tsec_info[num], 3);
338 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
339 tsec_info[num].flags |= TSEC_SGMII;
344 printf("No TSECs initialized\n");
350 fsl_sgmii_riser_init(tsec_info, num);
353 tsec_eth_init(bis, tsec_info, num);
355 return pci_eth_init(bis);
358 #if defined(CONFIG_OF_BOARD_SETUP)
359 void ft_board_setup(void *blob, bd_t *bd)
361 ft_cpu_setup(blob, bd);
365 #ifdef CONFIG_FSL_SGMII_RISER
366 fsl_sgmii_riser_fdt_fixup(blob);