git.sur5r.net Git - u-boot/blob - board/freescale/mpc8544ds/mpc8544ds.c

   1 /*
   2  * Copyright 2007 Freescale Semiconductor, Inc.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 #include <common.h>
  24 #include <command.h>
  25 #include <pci.h>
  26 #include <asm/processor.h>
  27 #include <asm/immap_85xx.h>
  28 #include <asm/immap_fsl_pci.h>
  29 #include <asm/io.h>
  30 #include <spd_sdram.h>
  31 #include <miiphy.h>
  32 #include <libfdt.h>
  33 #include <fdt_support.h>
  34
  35 #include "../common/pixis.h"
  36
  37 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
  38 extern void ddr_enable_ecc(unsigned int dram_size);
  39 #endif
  40
  41 void sdram_init(void);
  42
  43 int checkboard (void)
  44 {
  45         volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
  46         volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
  47         volatile ccsr_local_ecm_t *ecm = (void *)(CFG_MPC85xx_ECM_ADDR);
  48
  49         if ((uint)&gur->porpllsr != 0xe00e0000) {
  50                 printf("immap size error %lx\n",(ulong)&gur->porpllsr);
  51         }
  52         printf ("Board: MPC8544DS, System ID: 0x%02x, "
  53                 "System Version: 0x%02x, FPGA Version: 0x%02x\n",
  54                 in8(PIXIS_BASE + PIXIS_ID), in8(PIXIS_BASE + PIXIS_VER),
  55                 in8(PIXIS_BASE + PIXIS_PVER));
  56
  57         lbc->ltesr = 0xffffffff;        /* Clear LBC error interrupts */
  58         lbc->lteir = 0xffffffff;        /* Enable LBC error interrupts */
  59         ecm->eedr = 0xffffffff;         /* Clear ecm errors */
  60         ecm->eeer = 0xffffffff;         /* Enable ecm errors */
  61
  62         return 0;
  63 }
  64
  65 phys_size_t
  66 initdram(int board_type)
  67 {
  68         long dram_size = 0;
  69
  70         puts("Initializing\n");
  71
  72         dram_size = spd_sdram();
  73
  74 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
  75         /*
  76          * Initialize and enable DDR ECC.
  77          */
  78         ddr_enable_ecc(dram_size);
  79 #endif
  80         puts("    DDR: ");
  81         return dram_size;
  82 }
  83
  84 #ifdef CONFIG_PCI1
  85 static struct pci_controller pci1_hose;
  86 #endif
  87
  88 #ifdef CONFIG_PCIE1
  89 static struct pci_controller pcie1_hose;
  90 #endif
  91
  92 #ifdef CONFIG_PCIE2
  93 static struct pci_controller pcie2_hose;
  94 #endif
  95
  96 #ifdef CONFIG_PCIE3
  97 static struct pci_controller pcie3_hose;
  98 #endif
  99
 100 int first_free_busno=0;
 101
 102 void
 103 pci_init_board(void)
 104 {
 105         volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
 106         uint devdisr = gur->devdisr;
 107         uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
 108         uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
 109
 110         debug ("   pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n",
 111                 devdisr, io_sel, host_agent);
 112
 113         if (io_sel & 1) {
 114                 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS))
 115                         printf ("    eTSEC1 is in sgmii mode.\n");
 116                 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
 117                         printf ("    eTSEC3 is in sgmii mode.\n");
 118         }
 119
 120 #ifdef CONFIG_PCIE3
 121 {
 122         volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE3_ADDR;
 123         extern void fsl_pci_init(struct pci_controller *hose);
 124         struct pci_controller *hose = &pcie3_hose;
 125         int pcie_ep = (host_agent == 1);
 126         int pcie_configured  = io_sel >= 1;
 127
 128         if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
 129                 printf ("\n    PCIE3 connected to ULI as %s (base address %x)",
 130                         pcie_ep ? "End Point" : "Root Complex",
 131                         (uint)pci);
 132                 if (pci->pme_msg_det) {
 133                         pci->pme_msg_det = 0xffffffff;
 134                         debug (" with errors.  Clearing.  Now 0x%08x",pci->pme_msg_det);
 135                 }
 136                 printf ("\n");
 137
 138                 /* inbound */
 139                 pci_set_region(hose->regions + 0,
 140                                CFG_PCI_MEMORY_BUS,
 141                                CFG_PCI_MEMORY_PHYS,
 142                                CFG_PCI_MEMORY_SIZE,
 143                                PCI_REGION_MEM | PCI_REGION_MEMORY);
 144
 145                 /* outbound memory */
 146                 pci_set_region(hose->regions + 1,
 147                                CFG_PCIE3_MEM_BASE,
 148                                CFG_PCIE3_MEM_PHYS,
 149                                CFG_PCIE3_MEM_SIZE,
 150                                PCI_REGION_MEM);
 151
 152                 /* outbound io */
 153                 pci_set_region(hose->regions + 2,
 154                                CFG_PCIE3_IO_BASE,
 155                                CFG_PCIE3_IO_PHYS,
 156                                CFG_PCIE3_IO_SIZE,
 157                                PCI_REGION_IO);
 158
 159                 hose->region_count = 3;
 160 #ifdef CFG_PCIE3_MEM_BASE2
 161                 /* outbound memory */
 162                 pci_set_region(hose->regions + 3,
 163                                CFG_PCIE3_MEM_BASE2,
 164                                CFG_PCIE3_MEM_PHYS2,
 165                                CFG_PCIE3_MEM_SIZE2,
 166                                PCI_REGION_MEM);
 167                 hose->region_count++;
 168 #endif
 169                 hose->first_busno=first_free_busno;
 170                 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
 171
 172                 fsl_pci_init(hose);
 173
 174                 first_free_busno=hose->last_busno+1;
 175                 printf ("    PCIE3 on bus %02x - %02x\n",
 176                         hose->first_busno,hose->last_busno);
 177
 178                 /*
 179                  * Activate ULI1575 legacy chip by performing a fake
 180                  * memory access.  Needed to make ULI RTC work.
 181                  */
 182                 in_be32((u32 *)CFG_PCIE3_MEM_BASE);
 183         } else {
 184                 printf ("    PCIE3: disabled\n");
 185         }
 186
 187  }
 188 #else
 189         gur->devdisr |= MPC85xx_DEVDISR_PCIE3; /* disable */
 190 #endif
 191
 192 #ifdef CONFIG_PCIE1
 193  {
 194         volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE1_ADDR;
 195         extern void fsl_pci_init(struct pci_controller *hose);
 196         struct pci_controller *hose = &pcie1_hose;
 197         int pcie_ep = (host_agent == 5);
 198         int pcie_configured  = io_sel & 6;
 199
 200         if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
 201                 printf ("\n    PCIE1 connected to Slot2 as %s (base address %x)",
 202                         pcie_ep ? "End Point" : "Root Complex",
 203                         (uint)pci);
 204                 if (pci->pme_msg_det) {
 205                         pci->pme_msg_det = 0xffffffff;
 206                         debug (" with errors.  Clearing.  Now 0x%08x",pci->pme_msg_det);
 207                 }
 208                 printf ("\n");
 209
 210                 /* inbound */
 211                 pci_set_region(hose->regions + 0,
 212                                CFG_PCI_MEMORY_BUS,
 213                                CFG_PCI_MEMORY_PHYS,
 214                                CFG_PCI_MEMORY_SIZE,
 215                                PCI_REGION_MEM | PCI_REGION_MEMORY);
 216
 217                 /* outbound memory */
 218                 pci_set_region(hose->regions + 1,
 219                                CFG_PCIE1_MEM_BASE,
 220                                CFG_PCIE1_MEM_PHYS,
 221                                CFG_PCIE1_MEM_SIZE,
 222                                PCI_REGION_MEM);
 223
 224                 /* outbound io */
 225                 pci_set_region(hose->regions + 2,
 226                                CFG_PCIE1_IO_BASE,
 227                                CFG_PCIE1_IO_PHYS,
 228                                CFG_PCIE1_IO_SIZE,
 229                                PCI_REGION_IO);
 230
 231                 hose->region_count = 3;
 232 #ifdef CFG_PCIE1_MEM_BASE2
 233                 /* outbound memory */
 234                 pci_set_region(hose->regions + 3,
 235                                CFG_PCIE1_MEM_BASE2,
 236                                CFG_PCIE1_MEM_PHYS2,
 237                                CFG_PCIE1_MEM_SIZE2,
 238                                PCI_REGION_MEM);
 239                 hose->region_count++;
 240 #endif
 241                 hose->first_busno=first_free_busno;
 242
 243                 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
 244
 245                 fsl_pci_init(hose);
 246
 247                 first_free_busno=hose->last_busno+1;
 248                 printf("    PCIE1 on bus %02x - %02x\n",
 249                        hose->first_busno,hose->last_busno);
 250
 251         } else {
 252                 printf ("    PCIE1: disabled\n");
 253         }
 254
 255  }
 256 #else
 257         gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
 258 #endif
 259
 260 #ifdef CONFIG_PCIE2
 261  {
 262         volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE2_ADDR;
 263         extern void fsl_pci_init(struct pci_controller *hose);
 264         struct pci_controller *hose = &pcie2_hose;
 265         int pcie_ep = (host_agent == 3);
 266         int pcie_configured  = io_sel & 4;
 267
 268         if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
 269                 printf ("\n    PCIE2 connected to Slot 1 as %s (base address %x)",
 270                         pcie_ep ? "End Point" : "Root Complex",
 271                         (uint)pci);
 272                 if (pci->pme_msg_det) {
 273                         pci->pme_msg_det = 0xffffffff;
 274                         debug (" with errors.  Clearing.  Now 0x%08x",pci->pme_msg_det);
 275                 }
 276                 printf ("\n");
 277
 278                 /* inbound */
 279                 pci_set_region(hose->regions + 0,
 280                                CFG_PCI_MEMORY_BUS,
 281                                CFG_PCI_MEMORY_PHYS,
 282                                CFG_PCI_MEMORY_SIZE,
 283                                PCI_REGION_MEM | PCI_REGION_MEMORY);
 284
 285                 /* outbound memory */
 286                 pci_set_region(hose->regions + 1,
 287                                CFG_PCIE2_MEM_BASE,
 288                                CFG_PCIE2_MEM_PHYS,
 289                                CFG_PCIE2_MEM_SIZE,
 290                                PCI_REGION_MEM);
 291
 292                 /* outbound io */
 293                 pci_set_region(hose->regions + 2,
 294                                CFG_PCIE2_IO_BASE,
 295                                CFG_PCIE2_IO_PHYS,
 296                                CFG_PCIE2_IO_SIZE,
 297                                PCI_REGION_IO);
 298
 299                 hose->region_count = 3;
 300 #ifdef CFG_PCIE2_MEM_BASE2
 301                 /* outbound memory */
 302                 pci_set_region(hose->regions + 3,
 303                                CFG_PCIE2_MEM_BASE2,
 304                                CFG_PCIE2_MEM_PHYS2,
 305                                CFG_PCIE2_MEM_SIZE2,
 306                                PCI_REGION_MEM);
 307                 hose->region_count++;
 308 #endif
 309                 hose->first_busno=first_free_busno;
 310                 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
 311
 312                 fsl_pci_init(hose);
 313                 first_free_busno=hose->last_busno+1;
 314                 printf ("    PCIE2 on bus %02x - %02x\n",
 315                         hose->first_busno,hose->last_busno);
 316
 317         } else {
 318                 printf ("    PCIE2: disabled\n");
 319         }
 320
 321  }
 322 #else
 323         gur->devdisr |= MPC85xx_DEVDISR_PCIE2; /* disable */
 324 #endif
 325
 326
 327 #ifdef CONFIG_PCI1
 328 {
 329         volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR;
 330         extern void fsl_pci_init(struct pci_controller *hose);
 331         struct pci_controller *hose = &pci1_hose;
 332
 333         uint pci_agent = (host_agent == 6);
 334         uint pci_speed = 66666000; /*get_clock_freq (); PCI PSPEED in [4:5] */
 335         uint pci_32 = 1;
 336         uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;       /* PORDEVSR[14] */
 337         uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;   /* PORPLLSR[16] */
 338
 339
 340         if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
 341                 printf ("\n    PCI: %d bit, %s MHz, %s, %s, %s (base address %x)\n",
 342                         (pci_32) ? 32 : 64,
 343                         (pci_speed == 33333000) ? "33" :
 344                         (pci_speed == 66666000) ? "66" : "unknown",
 345                         pci_clk_sel ? "sync" : "async",
 346                         pci_agent ? "agent" : "host",
 347                         pci_arb ? "arbiter" : "external-arbiter",
 348                         (uint)pci
 349                         );
 350
 351                 /* inbound */
 352                 pci_set_region(hose->regions + 0,
 353                                CFG_PCI_MEMORY_BUS,
 354                                CFG_PCI_MEMORY_PHYS,
 355                                CFG_PCI_MEMORY_SIZE,
 356                                PCI_REGION_MEM | PCI_REGION_MEMORY);
 357
 358                 /* outbound memory */
 359                 pci_set_region(hose->regions + 1,
 360                                CFG_PCI1_MEM_BASE,
 361                                CFG_PCI1_MEM_PHYS,
 362                                CFG_PCI1_MEM_SIZE,
 363                                PCI_REGION_MEM);
 364
 365                 /* outbound io */
 366                 pci_set_region(hose->regions + 2,
 367                                CFG_PCI1_IO_BASE,
 368                                CFG_PCI1_IO_PHYS,
 369                                CFG_PCI1_IO_SIZE,
 370                                PCI_REGION_IO);
 371                 hose->region_count = 3;
 372 #ifdef CFG_PCIE3_MEM_BASE2
 373                 /* outbound memory */
 374                 pci_set_region(hose->regions + 3,
 375                                CFG_PCIE3_MEM_BASE2,
 376                                CFG_PCIE3_MEM_PHYS2,
 377                                CFG_PCIE3_MEM_SIZE2,
 378                                PCI_REGION_MEM);
 379                 hose->region_count++;
 380 #endif
 381                 hose->first_busno=first_free_busno;
 382                 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
 383
 384                 fsl_pci_init(hose);
 385                 first_free_busno=hose->last_busno+1;
 386                 printf ("PCI on bus %02x - %02x\n",
 387                         hose->first_busno,hose->last_busno);
 388         } else {
 389                 printf ("    PCI: disabled\n");
 390         }
 391 }
 392 #else
 393         gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */
 394 #endif
 395 }
 396
 397
 398 int last_stage_init(void)
 399 {
 400         return 0;
 401 }
 402
 403
 404 unsigned long
 405 get_board_sys_clk(ulong dummy)
 406 {
 407         u8 i, go_bit, rd_clks;
 408         ulong val = 0;
 409
 410         go_bit = in8(PIXIS_BASE + PIXIS_VCTL);
 411         go_bit &= 0x01;
 412
 413         rd_clks = in8(PIXIS_BASE + PIXIS_VCFGEN0);
 414         rd_clks &= 0x1C;
 415
 416         /*
 417          * Only if both go bit and the SCLK bit in VCFGEN0 are set
 418          * should we be using the AUX register. Remember, we also set the
 419          * GO bit to boot from the alternate bank on the on-board flash
 420          */
 421
 422         if (go_bit) {
 423                 if (rd_clks == 0x1c)
 424                         i = in8(PIXIS_BASE + PIXIS_AUX);
 425                 else
 426                         i = in8(PIXIS_BASE + PIXIS_SPD);
 427         } else {
 428                 i = in8(PIXIS_BASE + PIXIS_SPD);
 429         }
 430
 431         i &= 0x07;
 432
 433         switch (i) {
 434         case 0:
 435                 val = 33333333;
 436                 break;
 437         case 1:
 438                 val = 40000000;
 439                 break;
 440         case 2:
 441                 val = 50000000;
 442                 break;
 443         case 3:
 444                 val = 66666666;
 445                 break;
 446         case 4:
 447                 val = 83000000;
 448                 break;
 449         case 5:
 450                 val = 100000000;
 451                 break;
 452         case 6:
 453                 val = 133333333;
 454                 break;
 455         case 7:
 456                 val = 166666666;
 457                 break;
 458         }
 459
 460         return val;
 461 }
 462
 463 #if defined(CONFIG_OF_BOARD_SETUP)
 464
 465 void
 466 ft_board_setup(void *blob, bd_t *bd)
 467 {
 468         int node, tmp[2];
 469         const char *path;
 470
 471         ft_cpu_setup(blob, bd);
 472
 473         node = fdt_path_offset(blob, "/aliases");
 474         tmp[0] = 0;
 475         if (node >= 0) {
 476 #ifdef CONFIG_PCI1
 477                 path = fdt_getprop(blob, node, "pci0", NULL);
 478                 if (path) {
 479                         tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno;
 480                         do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
 481                 }
 482 #endif
 483 #ifdef CONFIG_PCIE2
 484                 path = fdt_getprop(blob, node, "pci1", NULL);
 485                 if (path) {
 486                         tmp[1] = pcie2_hose.last_busno - pcie2_hose.first_busno;
 487                         do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
 488                 }
 489 #endif
 490 #ifdef CONFIG_PCIE1
 491                 path = fdt_getprop(blob, node, "pci2", NULL);
 492                 if (path) {
 493                         tmp[1] = pcie1_hose.last_busno - pcie1_hose.first_busno;
 494                         do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
 495                 }
 496 #endif
 497 #ifdef CONFIG_PCIE3
 498                 path = fdt_getprop(blob, node, "pci3", NULL);
 499                 if (path) {
 500                         tmp[1] = pcie3_hose.last_busno - pcie3_hose.first_busno;
 501                         do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
 502                 }
 503 #endif
 504         }
 505 }
 506 #endif