2 * Copyright 2007 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/processor.h>
27 #include <asm/immap_85xx.h>
28 #include <asm/immap_fsl_pci.h>
32 #include "../common/pixis.h"
34 #if defined(CONFIG_OF_FLAT_TREE)
36 extern void ft_cpu_setup(void *blob, bd_t *bd);
39 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
40 extern void ddr_enable_ecc(unsigned int dram_size);
43 extern long int spd_sdram(void);
45 void sdram_init(void);
47 int board_early_init_f (void)
54 volatile immap_t *immap = (immap_t *) CFG_CCSRBAR;
55 volatile ccsr_gur_t *gur = &immap->im_gur;
56 volatile ccsr_lbc_t *lbc = &immap->im_lbc;
57 volatile ccsr_local_ecm_t *ecm = &immap->im_local_ecm;
59 if ((uint)&gur->porpllsr != 0xe00e0000) {
60 printf("immap size error %x\n",&gur->porpllsr);
62 printf ("Board: MPC8544DS\n");
64 lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */
65 lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */
66 ecm->eedr = 0xffffffff; /* Clear ecm errors */
67 ecm->eeer = 0xffffffff; /* Enable ecm errors */
73 initdram(int board_type)
77 puts("Initializing\n");
79 dram_size = spd_sdram();
81 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
83 * Initialize and enable DDR ECC.
85 ddr_enable_ecc(dram_size);
91 #if defined(CFG_DRAM_TEST)
95 uint *pstart = (uint *) CFG_MEMTEST_START;
96 uint *pend = (uint *) CFG_MEMTEST_END;
99 printf("Testing DRAM from 0x%08x to 0x%08x\n",
103 printf("DRAM test phase 1:\n");
104 for (p = pstart; p < pend; p++)
107 for (p = pstart; p < pend; p++) {
108 if (*p != 0xaaaaaaaa) {
109 printf ("DRAM test fails at: %08x\n", (uint) p);
114 printf("DRAM test phase 2:\n");
115 for (p = pstart; p < pend; p++)
118 for (p = pstart; p < pend; p++) {
119 if (*p != 0x55555555) {
120 printf ("DRAM test fails at: %08x\n", (uint) p);
125 printf("DRAM test passed.\n");
131 static struct pci_controller pci1_hose;
135 static struct pci_controller pcie1_hose;
139 static struct pci_controller pcie2_hose;
143 static struct pci_controller pcie3_hose;
146 int first_free_busno=0;
151 volatile immap_t *immap = (immap_t *)CFG_IMMR;
152 volatile ccsr_gur_t *gur = &immap->im_gur;
153 uint devdisr = gur->devdisr;
154 uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
155 uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
157 debug (" pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n",
158 devdisr, io_sel, host_agent);
161 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS))
162 printf (" eTSEC1 is in sgmii mode.\n");
163 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
164 printf (" eTSEC3 is in sgmii mode.\n");
169 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE3_ADDR;
170 extern void fsl_pci_init(struct pci_controller *hose);
171 struct pci_controller *hose = &pcie3_hose;
172 int pcie_ep = (host_agent == 3);
173 int pcie_configured = io_sel >= 1;
175 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
176 printf ("\n PCIE3 connected to ULI as %s (base address %x)",
177 pcie_ep ? "End Point" : "Root Complex",
179 if (pci->pme_msg_det) {
180 pci->pme_msg_det = 0xffffffff;
181 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
186 pci_set_region(hose->regions + 0,
190 PCI_REGION_MEM | PCI_REGION_MEMORY);
192 /* outbound memory */
193 pci_set_region(hose->regions + 1,
200 pci_set_region(hose->regions + 2,
206 hose->region_count = 3;
207 #ifdef CFG_PCIE3_MEM_BASE2
208 /* outbound memory */
209 pci_set_region(hose->regions + 3,
214 hose->region_count++;
216 hose->first_busno=first_free_busno;
217 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
221 first_free_busno=hose->last_busno+1;
222 printf (" PCIE3 on bus %02x - %02x\n",
223 hose->first_busno,hose->last_busno);
226 printf (" PCIE3: disabled\n");
231 gur->devdisr |= MPC85xx_DEVDISR_PCIE3; /* disable */
236 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE1_ADDR;
237 extern void fsl_pci_init(struct pci_controller *hose);
238 struct pci_controller *hose = &pcie1_hose;
239 int pcie_ep = (host_agent == 5);
240 int pcie_configured = io_sel & 6;
242 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
243 printf ("\n PCIE1 connected to Slot2 as %s (base address %x)",
244 pcie_ep ? "End Point" : "Root Complex",
246 if (pci->pme_msg_det) {
247 pci->pme_msg_det = 0xffffffff;
248 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
253 pci_set_region(hose->regions + 0,
257 PCI_REGION_MEM | PCI_REGION_MEMORY);
259 /* outbound memory */
260 pci_set_region(hose->regions + 1,
267 pci_set_region(hose->regions + 2,
273 hose->region_count = 3;
274 #ifdef CFG_PCIE1_MEM_BASE2
275 /* outbound memory */
276 pci_set_region(hose->regions + 3,
281 hose->region_count++;
283 hose->first_busno=first_free_busno;
285 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
289 first_free_busno=hose->last_busno+1;
290 printf(" PCIE1 on bus %02x - %02x\n",
291 hose->first_busno,hose->last_busno);
294 printf (" PCIE1: disabled\n");
299 gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
304 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE2_ADDR;
305 extern void fsl_pci_init(struct pci_controller *hose);
306 struct pci_controller *hose = &pcie2_hose;
307 int pcie_ep = (host_agent == 3);
308 int pcie_configured = io_sel & 4;
310 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
311 printf ("\n PCIE2 connected to Slot 1 as %s (base address %x)",
312 pcie_ep ? "End Point" : "Root Complex",
314 if (pci->pme_msg_det) {
315 pci->pme_msg_det = 0xffffffff;
316 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
321 pci_set_region(hose->regions + 0,
325 PCI_REGION_MEM | PCI_REGION_MEMORY);
327 /* outbound memory */
328 pci_set_region(hose->regions + 1,
335 pci_set_region(hose->regions + 2,
341 hose->region_count = 3;
342 #ifdef CFG_PCIE2_MEM_BASE2
343 /* outbound memory */
344 pci_set_region(hose->regions + 3,
349 hose->region_count++;
351 hose->first_busno=first_free_busno;
352 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
355 first_free_busno=hose->last_busno+1;
356 printf (" PCIE2 on bus %02x - %02x\n",
357 hose->first_busno,hose->last_busno);
360 printf (" PCIE2: disabled\n");
365 gur->devdisr |= MPC85xx_DEVDISR_PCIE2; /* disable */
371 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR;
372 extern void fsl_pci_init(struct pci_controller *hose);
373 struct pci_controller *hose = &pci1_hose;
375 uint pci_agent = (host_agent == 6);
376 uint pci_speed = 66666000; /*get_clock_freq (); PCI PSPEED in [4:5] */
378 uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */
379 uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */
382 if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
383 printf ("\n PCI: %d bit, %s MHz, %s, %s, %s (base address %x)\n",
385 (pci_speed == 33333000) ? "33" :
386 (pci_speed == 66666000) ? "66" : "unknown",
387 pci_clk_sel ? "sync" : "async",
388 pci_agent ? "agent" : "host",
389 pci_arb ? "arbiter" : "external-arbiter",
394 pci_set_region(hose->regions + 0,
398 PCI_REGION_MEM | PCI_REGION_MEMORY);
400 /* outbound memory */
401 pci_set_region(hose->regions + 1,
408 pci_set_region(hose->regions + 2,
413 hose->region_count = 3;
414 #ifdef CFG_PCIE3_MEM_BASE2
415 /* outbound memory */
416 pci_set_region(hose->regions + 3,
421 hose->region_count++;
423 hose->first_busno=first_free_busno;
424 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
427 first_free_busno=hose->last_busno+1;
428 printf ("PCI on bus %02x - %02x\n",
429 hose->first_busno,hose->last_busno);
431 printf (" PCI: disabled\n");
435 gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */
440 int last_stage_init(void)
447 get_board_sys_clk(ulong dummy)
449 u8 i, go_bit, rd_clks;
452 go_bit = in8(PIXIS_BASE + PIXIS_VCTL);
455 rd_clks = in8(PIXIS_BASE + PIXIS_VCFGEN0);
459 * Only if both go bit and the SCLK bit in VCFGEN0 are set
460 * should we be using the AUX register. Remember, we also set the
461 * GO bit to boot from the alternate bank on the on-board flash
466 i = in8(PIXIS_BASE + PIXIS_AUX);
468 i = in8(PIXIS_BASE + PIXIS_SPD);
470 i = in8(PIXIS_BASE + PIXIS_SPD);
505 #if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
507 ft_board_setup(void *blob, bd_t *bd)
512 ft_cpu_setup(blob, bd);
514 p = ft_get_prop(blob, "/memory/reg", &len);
516 *p++ = cpu_to_be32(bd->bi_memstart);
517 *p = cpu_to_be32(bd->bi_memsize);
520 p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@a000/bus-range", &len);
523 p[1] = pcie1_hose.last_busno - pcie1_hose.first_busno;
524 debug("PCI@a000 first_busno=%d last_busno=%d\n",p[0],p[1]);
528 p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@9000/bus-range", &len);
531 p[1] = pcie2_hose.last_busno - pcie2_hose.first_busno;
532 debug("PCI@9000 first_busno=%d last_busno=%d\n",p[0],p[1]);
536 p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@b000/bus-range", &len);
539 p[1] = pcie3_hose.last_busno - pcie3_hose.first_busno;;
540 debug("PCI@b000 first_busno=%d last_busno=%d\n",p[0],p[1]);