2 * Copyright 2004, 2007 Freescale Semiconductor.
3 * Copyright 2002,2003, Motorola Inc.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 #include <ppc_asm.tmpl>
26 #include <asm/cache.h>
32 * TLB0 and TLB1 Entries
34 * Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR.
35 * However, CCSRBAR is then relocated to CFG_CCSRBAR right after
36 * these TLB entries are established.
38 * The TLB entries for DDR are dynamically setup in spd_sdram()
39 * and use TLB1 Entries 8 through 15 as needed according to the
42 * MAS0: tlbsel, esel, nv
43 * MAS1: valid, iprot, tid, ts, tsize
44 * MAS2: epn, x0, x1, w, i, m, g, e
45 * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr
58 .section .bootpg, "ax"
64 * Number of TLB0 and TLB1 entries in the following table
69 #if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
71 * TLB0 4K Non-cacheable, guarded
72 * 0xff700000 4K Initial CCSRBAR mapping
74 * This ends up at a TLB0 Index==0 entry, and must not collide
75 * with other TLB0 Entries.
77 .long FSL_BOOKE_MAS0(0, 0, 0)
78 .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
79 .long FSL_BOOKE_MAS2(CFG_CCSRBAR_DEFAULT, (MAS2_I|MAS2_G))
80 .long FSL_BOOKE_MAS3(CFG_CCSRBAR_DEFAULT, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
82 #error("Update the number of table entries in tlb1_entry")
86 * TLB0 16K Cacheable, guarded
87 * Temporary Global data for initialization
89 * Use four 4K TLB0 entries. These entries must be cacheable
90 * as they provide the bootstrap memory before the memory
91 * controler and real memory have been configured.
93 * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c,
94 * and must not collide with other TLB0 entries.
96 .long FSL_BOOKE_MAS0(0, 0, 0)
97 .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
98 .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR, (MAS2_G))
99 .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
101 .long FSL_BOOKE_MAS0(0, 0, 0)
102 .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
103 .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 4 * 1024, (MAS2_G))
104 .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 4 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
106 .long FSL_BOOKE_MAS0(0, 0, 0)
107 .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
108 .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 8 * 1024, (MAS2_G))
109 .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 8 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
111 .long FSL_BOOKE_MAS0(0, 0, 0)
112 .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
113 .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 12 * 1024, (MAS2_G))
114 .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 12 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
118 * TLB 0: 16M Non-cacheable, guarded
119 * 0xff000000 16M FLASH
120 * Out of reset this entry is only 4K.
122 .long FSL_BOOKE_MAS0(1, 0, 0)
123 .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)
124 .long FSL_BOOKE_MAS2(CFG_BOOT_BLOCK, (MAS2_I|MAS2_G))
125 .long FSL_BOOKE_MAS3(CFG_BOOT_BLOCK, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
128 * TLB 1: 1G Non-cacheable, guarded
129 * 0x80000000 1G PCI1/PCIE 8,9,a,b
131 .long FSL_BOOKE_MAS0(1, 1, 0)
132 .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1G)
133 .long FSL_BOOKE_MAS2(CFG_PCI_PHYS, (MAS2_I|MAS2_G))
134 .long FSL_BOOKE_MAS3(CFG_PCI_PHYS, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
136 #ifdef CFG_RIO_MEM_PHYS
138 * TLB 2: 256M Non-cacheable, guarded
140 .long FSL_BOOKE_MAS0(1, 2, 0)
141 .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
142 .long FSL_BOOKE_MAS2(CFG_RIO_MEM_PHYS, (MAS2_I|MAS2_G))
143 .long FSL_BOOKE_MAS3(CFG_RIO_MEM_PHYS, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
146 * TLB 3: 256M Non-cacheable, guarded
148 .long FSL_BOOKE_MAS0(1, 3, 0)
149 .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
150 .long FSL_BOOKE_MAS2(CFG_RIO_MEM_PHYS + 0x10000000, (MAS2_I|MAS2_G))
151 .long FSL_BOOKE_MAS3(CFG_RIO_MEM_PHYS + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
154 * TLB 5: 64M Non-cacheable, guarded
155 * 0xe000_0000 1M CCSRBAR
156 * 0xe200_0000 1M PCI1 IO
157 * 0xe210_0000 1M PCI2 IO
158 * 0xe300_0000 1M PCIe IO
160 .long FSL_BOOKE_MAS0(1, 5, 0)
161 .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
162 .long FSL_BOOKE_MAS2(CFG_CCSRBAR, (MAS2_I|MAS2_G))
163 .long FSL_BOOKE_MAS3(CFG_CCSRBAR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
166 * TLB 6: 64M Cacheable, non-guarded
167 * 0xf000_0000 64M LBC SDRAM
169 .long FSL_BOOKE_MAS0(1, 6, 0)
170 .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
171 .long FSL_BOOKE_MAS2(CFG_LBC_CACHE_BASE, 0)
172 .long FSL_BOOKE_MAS3(CFG_LBC_CACHE_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
175 * TLB 7: 64M Non-cacheable, guarded
176 * 0xf8000000 64M CADMUS registers, relocated L2SRAM
178 .long FSL_BOOKE_MAS0(1, 7, 0)
179 .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
180 .long FSL_BOOKE_MAS2(CFG_LBC_NONCACHE_BASE, (MAS2_I|MAS2_G))
181 .long FSL_BOOKE_MAS3(CFG_LBC_NONCACHE_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
187 * LAW(Local Access Window) configuration:
189 * 0x0000_0000 0x7fff_ffff DDR 2G
190 * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
191 * 0xa000_0000 0xbfff_ffff PCIe MEM 512M
192 * 0xc000_0000 0xdfff_ffff RapidIO 512M
193 * 0xe000_0000 0xe000_ffff CCSR 1M
194 * 0xe200_0000 0xe10f_ffff PCI1 IO 1M
195 * 0xe280_0000 0xe20f_ffff PCI2 IO 1M
196 * 0xe300_0000 0xe30f_ffff PCIe IO 1M
197 * 0xf000_0000 0xf3ff_ffff SDRAM 64M
198 * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M
199 * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M
200 * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M
203 * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
204 * If flash is 8M at default position (last 8M), no LAW needed.
206 * LAW 0 is reserved for boot mapping
209 .section .bootpg, "ax"
217 .long (LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN
219 #ifdef CFG_PCI1_MEM_PHYS
220 .long (CFG_PCI1_MEM_PHYS>>12) & 0xfffff
221 .long LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M)
223 .long (CFG_PCI1_IO_PHYS>>12) & 0xfffff
224 .long LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_1M)
227 #ifdef CFG_PCI2_MEM_PHYS
228 .long (CFG_PCI2_MEM_PHYS>>12) & 0xfffff
229 .long LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M)
231 .long (CFG_PCI2_IO_PHYS>>12) & 0xfffff
232 .long LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_1M)
235 #ifdef CFG_PCIE1_MEM_PHYS
236 .long (CFG_PCIE1_MEM_PHYS>>12) & 0xfffff
237 .long LAWAR_EN | LAWAR_TRGT_IF_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_512M)
239 .long (CFG_PCIE1_IO_PHYS>>12) & 0xfffff
240 .long LAWAR_EN | LAWAR_TRGT_IF_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_1M)
243 /* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
244 .long (CFG_LBC_CACHE_BASE>>12) & 0xfffff
245 .long LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M)
247 #ifdef CFG_RIO_MEM_PHYS
248 .long (CFG_RIO_MEM_PHYS>>12) & 0xfffff
249 .long LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M)