2 * Copyright 2004, 2007 Freescale Semiconductor.
4 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 #include <asm/processor.h>
28 #include <asm/immap_85xx.h>
29 #include <asm/immap_fsl_pci.h>
30 #include <spd_sdram.h>
33 #include <fdt_support.h>
35 #include "../common/cadmus.h"
36 #include "../common/eeprom.h"
37 #include "../common/via.h"
39 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
40 extern void ddr_enable_ecc(unsigned int dram_size);
43 DECLARE_GLOBAL_DATA_PTR;
45 void local_bus_init(void);
46 void sdram_init(void);
50 volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
51 volatile ccsr_local_ecm_t *ecm = (void *)(CFG_MPC85xx_ECM_ADDR);
53 /* PCI slot in USER bits CSR[6:7] by convention. */
54 uint pci_slot = get_pci_slot ();
56 uint cpu_board_rev = get_cpu_board_revision ();
59 printf ("Board: CDS Version 0x%02x, PCI Slot %d\n",
60 get_board_version (), pci_slot);
62 printf ("CPU Board Revision %d.%d (0x%04x)\n",
63 MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev),
64 MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev);
66 * Initialize local bus.
73 * Fix CPU2 errata: A core hang possible while executing a
74 * msync instruction and a snoopable transaction from an I/O
75 * master tagged to make quick forward progress is present.
76 * Fixed in Silicon Rev.2.1
78 if (!(SVR_MAJ(svr) >= 2 && SVR_MIN(svr) >= 1))
79 ecm->eebpcr |= (1 << 16);
82 * Hack TSEC 3 and 4 IO voltages.
84 gur->tsec34ioovcr = 0xe7e0; /* 1110 0111 1110 0xxx */
86 ecm->eedr = 0xffffffff; /* clear ecm errors */
87 ecm->eeer = 0xffffffff; /* enable ecm errors */
92 initdram(int board_type)
96 puts("Initializing\n");
98 #if defined(CONFIG_DDR_DLL)
101 * Work around to stabilize DDR DLL MSYNC_IN.
102 * Errata DDR9 seems to have been fixed.
103 * This is now the workaround for Errata DDR11:
104 * Override DLL = 1, Course Adj = 1, Tap Select = 0
107 volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
109 gur->ddrdllcr = 0x81000000;
110 asm("sync;isync;msync");
114 dram_size = spd_sdram();
116 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
118 * Initialize and enable DDR ECC.
120 ddr_enable_ecc(dram_size);
123 * SDRAM Initialization
132 * Initialize Local Bus
137 volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
138 volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
144 get_sys_info(&sysinfo);
145 clkdiv = (lbc->lcrr & 0x0f) * 2;
146 lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
148 gur->lbiuiplldcr1 = 0x00078080;
150 gur->lbiuiplldcr0 = 0x7c0f1bf0;
151 } else if (clkdiv == 8) {
152 gur->lbiuiplldcr0 = 0x6c0f1bf0;
153 } else if (clkdiv == 4) {
154 gur->lbiuiplldcr0 = 0x5c0f1bf0;
157 lbc->lcrr |= 0x00030000;
159 asm("sync;isync;msync");
161 lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */
162 lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */
166 * Initialize SDRAM memory on the Local Bus.
171 #if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM)
174 volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
175 uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
181 print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
184 * Setup SDRAM Base and Option Registers
186 lbc->or2 = CFG_OR2_PRELIM;
189 lbc->br2 = CFG_BR2_PRELIM;
192 lbc->lbcr = CFG_LBC_LBCR;
196 lbc->lsrt = CFG_LBC_LSRT;
197 lbc->mrtpr = CFG_LBC_MRTPR;
201 * MPC8548 uses "new" 15-16 style addressing.
203 cpu_board_rev = get_cpu_board_revision();
204 lsdmr_common = CFG_LBC_LSDMR_COMMON;
205 lsdmr_common |= CFG_LBC_LSDMR_BSMA1516;
208 * Issue PRECHARGE ALL command.
210 lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_PCHALL;
213 ppcDcbf((unsigned long) sdram_addr);
217 * Issue 8 AUTO REFRESH commands.
219 for (idx = 0; idx < 8; idx++) {
220 lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_ARFRSH;
223 ppcDcbf((unsigned long) sdram_addr);
228 * Issue 8 MODE-set command.
230 lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_MRW;
233 ppcDcbf((unsigned long) sdram_addr);
237 * Issue NORMAL OP command.
239 lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_NORMAL;
242 ppcDcbf((unsigned long) sdram_addr);
243 udelay(200); /* Overkill. Must wait > 200 bus cycles */
245 #endif /* enable SDRAM init */
248 #if defined(CONFIG_PCI) || defined(CONFIG_PCI1)
249 /* For some reason the Tundra PCI bridge shows up on itself as a
250 * different device. Work around that by refusing to configure it.
252 void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { }
254 static struct pci_config_table pci_mpc85xxcds_config_table[] = {
255 {0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}},
256 {0x1106, 0x0686, PCI_ANY_ID, 1, VIA_ID, 0, mpc85xx_config_via, {0,0,0}},
257 {0x1106, 0x0571, PCI_ANY_ID, 1, VIA_ID, 1,
258 mpc85xx_config_via_usbide, {0,0,0}},
259 {0x1105, 0x3038, PCI_ANY_ID, 1, VIA_ID, 2,
260 mpc85xx_config_via_usb, {0,0,0}},
261 {0x1106, 0x3038, PCI_ANY_ID, 1, VIA_ID, 3,
262 mpc85xx_config_via_usb2, {0,0,0}},
263 {0x1106, 0x3058, PCI_ANY_ID, 1, VIA_ID, 5,
264 mpc85xx_config_via_power, {0,0,0}},
265 {0x1106, 0x3068, PCI_ANY_ID, 1, VIA_ID, 6,
266 mpc85xx_config_via_ac97, {0,0,0}},
270 static struct pci_controller pci1_hose = {
271 config_table: pci_mpc85xxcds_config_table};
272 #endif /* CONFIG_PCI */
275 static struct pci_controller pci2_hose;
276 #endif /* CONFIG_PCI2 */
279 static struct pci_controller pcie1_hose;
280 #endif /* CONFIG_PCIE1 */
282 int first_free_busno=0;
287 volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
288 uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
289 uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
294 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR;
295 extern void fsl_pci_init(struct pci_controller *hose);
296 struct pci_controller *hose = &pci1_hose;
297 struct pci_config_table *table;
299 uint pci_32 = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32; /* PORDEVSR[15] */
300 uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */
301 uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */
303 uint pci_agent = (host_agent == 3) || (host_agent == 4 ) || (host_agent == 6);
305 uint pci_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */
307 if (!(gur->devdisr & MPC85xx_DEVDISR_PCI1)) {
308 printf (" PCI: %d bit, %s MHz, %s, %s, %s\n",
310 (pci_speed == 33333000) ? "33" :
311 (pci_speed == 66666000) ? "66" : "unknown",
312 pci_clk_sel ? "sync" : "async",
313 pci_agent ? "agent" : "host",
314 pci_arb ? "arbiter" : "external-arbiter"
319 pci_set_region(hose->regions + 0,
323 PCI_REGION_MEM | PCI_REGION_MEMORY);
326 /* outbound memory */
327 pci_set_region(hose->regions + 1,
334 pci_set_region(hose->regions + 2,
339 hose->region_count = 3;
341 /* relocate config table pointers */
342 hose->config_table = \
343 (struct pci_config_table *)((uint)hose->config_table + gd->reloc_off);
344 for (table = hose->config_table; table && table->vendor; table++)
345 table->config_device += gd->reloc_off;
347 hose->first_busno=first_free_busno;
348 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
351 first_free_busno=hose->last_busno+1;
352 printf ("PCI on bus %02x - %02x\n",hose->first_busno,hose->last_busno);
353 #ifdef CONFIG_PCIX_CHECK
354 if (!(gur->pordevsr & PORDEVSR_PCI)) {
356 if (CONFIG_SYS_CLK_FREQ < 66000000)
357 printf("PCI-X will only work at 66 MHz\n");
359 reg16 = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ
360 | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
361 pci_hose_write_config_word(hose, bus, PCIX_COMMAND, reg16);
365 printf (" PCI: disabled\n");
369 gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */
374 uint pci2_clk_sel = gur->porpllsr & 0x4000; /* PORPLLSR[17] */
375 uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */
377 printf (" PCI2: 32 bit, 66 MHz, %s\n",
378 pci2_clk_sel ? "sync" : "async");
380 printf (" PCI2: disabled\n");
384 gur->devdisr |= MPC85xx_DEVDISR_PCI2; /* disable */
385 #endif /* CONFIG_PCI2 */
389 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE1_ADDR;
390 extern void fsl_pci_init(struct pci_controller *hose);
391 struct pci_controller *hose = &pcie1_hose;
392 int pcie_ep = (host_agent == 0) || (host_agent == 2 ) || (host_agent == 3);
394 int pcie_configured = io_sel >= 1;
396 if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){
397 printf ("\n PCIE connected to slot as %s (base address %x)",
398 pcie_ep ? "End Point" : "Root Complex",
401 if (pci->pme_msg_det) {
402 pci->pme_msg_det = 0xffffffff;
403 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
408 pci_set_region(hose->regions + 0,
412 PCI_REGION_MEM | PCI_REGION_MEMORY);
414 /* outbound memory */
415 pci_set_region(hose->regions + 1,
422 pci_set_region(hose->regions + 2,
428 hose->region_count = 3;
430 hose->first_busno=first_free_busno;
431 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
434 printf ("PCIE on bus %d - %d\n",hose->first_busno,hose->last_busno);
436 first_free_busno=hose->last_busno+1;
439 printf (" PCIE: disabled\n");
443 gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
448 int last_stage_init(void)
452 /* Change the resistors for the PHY */
453 /* This is needed to get the RGMII working for the 1.3+
455 if (get_board_version() == 0x13) {
456 miiphy_write(CONFIG_TSEC1_NAME,
457 TSEC1_PHY_ADDR, 29, 18);
459 miiphy_read(CONFIG_TSEC1_NAME,
460 TSEC1_PHY_ADDR, 30, &temp);
462 temp = (temp & 0xf03f);
463 temp |= 2 << 9; /* 36 ohm */
464 temp |= 2 << 6; /* 39 ohm */
466 miiphy_write(CONFIG_TSEC1_NAME,
467 TSEC1_PHY_ADDR, 30, temp);
469 miiphy_write(CONFIG_TSEC1_NAME,
470 TSEC1_PHY_ADDR, 29, 3);
472 miiphy_write(CONFIG_TSEC1_NAME,
473 TSEC1_PHY_ADDR, 30, 0x8000);
480 #if defined(CONFIG_OF_BOARD_SETUP)
482 ft_pci_setup(void *blob, bd_t *bd)
487 node = fdt_path_offset(blob, "/aliases");
491 path = fdt_getprop(blob, node, "pci0", NULL);
493 tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno;
494 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
498 path = fdt_getprop(blob, node, "pci1", NULL);
500 tmp[1] = pcie1_hose.last_busno - pcie1_hose.first_busno;
501 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);