2 * Copyright 2004, 2007 Freescale Semiconductor.
4 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 #include <asm/processor.h>
28 #include <asm/immap_85xx.h>
29 #include <asm/immap_fsl_pci.h>
33 #include <fdt_support.h>
35 #include "../common/cadmus.h"
36 #include "../common/eeprom.h"
37 #include "../common/via.h"
39 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
40 extern void ddr_enable_ecc(unsigned int dram_size);
43 DECLARE_GLOBAL_DATA_PTR;
45 extern long int spd_sdram(void);
47 void local_bus_init(void);
48 void sdram_init(void);
50 int board_early_init_f (void)
57 volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
58 volatile ccsr_local_ecm_t *ecm = (void *)(CFG_MPC85xx_ECM_ADDR);
60 /* PCI slot in USER bits CSR[6:7] by convention. */
61 uint pci_slot = get_pci_slot ();
63 uint cpu_board_rev = get_cpu_board_revision ();
65 printf ("Board: CDS Version 0x%02x, PCI Slot %d\n",
66 get_board_version (), pci_slot);
68 printf ("CPU Board Revision %d.%d (0x%04x)\n",
69 MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev),
70 MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev);
72 * Initialize local bus.
77 * Fix CPU2 errata: A core hang possible while executing a
78 * msync instruction and a snoopable transaction from an I/O
79 * master tagged to make quick forward progress is present.
81 ecm->eebpcr |= (1 << 16);
84 * Hack TSEC 3 and 4 IO voltages.
86 gur->tsec34ioovcr = 0xe7e0; /* 1110 0111 1110 0xxx */
88 ecm->eedr = 0xffffffff; /* clear ecm errors */
89 ecm->eeer = 0xffffffff; /* enable ecm errors */
94 initdram(int board_type)
98 puts("Initializing\n");
100 #if defined(CONFIG_DDR_DLL)
103 * Work around to stabilize DDR DLL MSYNC_IN.
104 * Errata DDR9 seems to have been fixed.
105 * This is now the workaround for Errata DDR11:
106 * Override DLL = 1, Course Adj = 1, Tap Select = 0
109 volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
111 gur->ddrdllcr = 0x81000000;
112 asm("sync;isync;msync");
116 dram_size = spd_sdram();
118 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
120 * Initialize and enable DDR ECC.
122 ddr_enable_ecc(dram_size);
125 * SDRAM Initialization
134 * Initialize Local Bus
139 volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
140 volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
146 get_sys_info(&sysinfo);
147 clkdiv = (lbc->lcrr & 0x0f) * 2;
148 lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
150 gur->lbiuiplldcr1 = 0x00078080;
152 gur->lbiuiplldcr0 = 0x7c0f1bf0;
153 } else if (clkdiv == 8) {
154 gur->lbiuiplldcr0 = 0x6c0f1bf0;
155 } else if (clkdiv == 4) {
156 gur->lbiuiplldcr0 = 0x5c0f1bf0;
159 lbc->lcrr |= 0x00030000;
161 asm("sync;isync;msync");
163 lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */
164 lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */
168 * Initialize SDRAM memory on the Local Bus.
173 #if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM)
176 volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
177 uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
183 print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
186 * Setup SDRAM Base and Option Registers
188 lbc->or2 = CFG_OR2_PRELIM;
191 lbc->br2 = CFG_BR2_PRELIM;
194 lbc->lbcr = CFG_LBC_LBCR;
198 lbc->lsrt = CFG_LBC_LSRT;
199 lbc->mrtpr = CFG_LBC_MRTPR;
203 * MPC8548 uses "new" 15-16 style addressing.
205 cpu_board_rev = get_cpu_board_revision();
206 lsdmr_common = CFG_LBC_LSDMR_COMMON;
207 lsdmr_common |= CFG_LBC_LSDMR_BSMA1516;
210 * Issue PRECHARGE ALL command.
212 lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_PCHALL;
215 ppcDcbf((unsigned long) sdram_addr);
219 * Issue 8 AUTO REFRESH commands.
221 for (idx = 0; idx < 8; idx++) {
222 lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_ARFRSH;
225 ppcDcbf((unsigned long) sdram_addr);
230 * Issue 8 MODE-set command.
232 lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_MRW;
235 ppcDcbf((unsigned long) sdram_addr);
239 * Issue NORMAL OP command.
241 lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_NORMAL;
244 ppcDcbf((unsigned long) sdram_addr);
245 udelay(200); /* Overkill. Must wait > 200 bus cycles */
247 #endif /* enable SDRAM init */
250 #if defined(CFG_DRAM_TEST)
254 uint *pstart = (uint *) CFG_MEMTEST_START;
255 uint *pend = (uint *) CFG_MEMTEST_END;
258 printf("Testing DRAM from 0x%08x to 0x%08x\n",
262 printf("DRAM test phase 1:\n");
263 for (p = pstart; p < pend; p++)
266 for (p = pstart; p < pend; p++) {
267 if (*p != 0xaaaaaaaa) {
268 printf ("DRAM test fails at: %08x\n", (uint) p);
273 printf("DRAM test phase 2:\n");
274 for (p = pstart; p < pend; p++)
277 for (p = pstart; p < pend; p++) {
278 if (*p != 0x55555555) {
279 printf ("DRAM test fails at: %08x\n", (uint) p);
284 printf("DRAM test passed.\n");
289 #if defined(CONFIG_PCI) || defined(CONFIG_PCI1)
290 /* For some reason the Tundra PCI bridge shows up on itself as a
291 * different device. Work around that by refusing to configure it.
293 void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { }
295 static struct pci_config_table pci_mpc85xxcds_config_table[] = {
296 {0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}},
297 {0x1106, 0x0686, PCI_ANY_ID, 1, VIA_ID, 0, mpc85xx_config_via, {0,0,0}},
298 {0x1106, 0x0571, PCI_ANY_ID, 1, VIA_ID, 1,
299 mpc85xx_config_via_usbide, {0,0,0}},
300 {0x1105, 0x3038, PCI_ANY_ID, 1, VIA_ID, 2,
301 mpc85xx_config_via_usb, {0,0,0}},
302 {0x1106, 0x3038, PCI_ANY_ID, 1, VIA_ID, 3,
303 mpc85xx_config_via_usb2, {0,0,0}},
304 {0x1106, 0x3058, PCI_ANY_ID, 1, VIA_ID, 5,
305 mpc85xx_config_via_power, {0,0,0}},
306 {0x1106, 0x3068, PCI_ANY_ID, 1, VIA_ID, 6,
307 mpc85xx_config_via_ac97, {0,0,0}},
311 static struct pci_controller pci1_hose = {
312 config_table: pci_mpc85xxcds_config_table};
313 #endif /* CONFIG_PCI */
316 static struct pci_controller pci2_hose;
317 #endif /* CONFIG_PCI2 */
320 static struct pci_controller pcie1_hose;
321 #endif /* CONFIG_PCIE1 */
323 int first_free_busno=0;
328 volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
329 uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
330 uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
335 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR;
336 extern void fsl_pci_init(struct pci_controller *hose);
337 struct pci_controller *hose = &pci1_hose;
338 struct pci_config_table *table;
340 uint pci_32 = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32; /* PORDEVSR[15] */
341 uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */
342 uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */
344 uint pci_agent = (host_agent == 3) || (host_agent == 4 ) || (host_agent == 6);
346 uint pci_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */
348 if (!(gur->devdisr & MPC85xx_DEVDISR_PCI1)) {
349 printf (" PCI: %d bit, %s MHz, %s, %s, %s\n",
351 (pci_speed == 33333000) ? "33" :
352 (pci_speed == 66666000) ? "66" : "unknown",
353 pci_clk_sel ? "sync" : "async",
354 pci_agent ? "agent" : "host",
355 pci_arb ? "arbiter" : "external-arbiter"
360 pci_set_region(hose->regions + 0,
364 PCI_REGION_MEM | PCI_REGION_MEMORY);
367 /* outbound memory */
368 pci_set_region(hose->regions + 1,
375 pci_set_region(hose->regions + 2,
380 hose->region_count = 3;
382 /* relocate config table pointers */
383 hose->config_table = \
384 (struct pci_config_table *)((uint)hose->config_table + gd->reloc_off);
385 for (table = hose->config_table; table && table->vendor; table++)
386 table->config_device += gd->reloc_off;
388 hose->first_busno=first_free_busno;
389 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
392 first_free_busno=hose->last_busno+1;
393 printf ("PCI on bus %02x - %02x\n",hose->first_busno,hose->last_busno);
394 #ifdef CONFIG_PCIX_CHECK
395 if (!(gur->pordevsr & PORDEVSR_PCI)) {
397 if (CONFIG_SYS_CLK_FREQ < 66000000)
398 printf("PCI-X will only work at 66 MHz\n");
400 reg16 = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ
401 | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
402 pci_hose_write_config_word(hose, bus, PCIX_COMMAND, reg16);
406 printf (" PCI: disabled\n");
410 gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */
415 uint pci2_clk_sel = gur->porpllsr & 0x4000; /* PORPLLSR[17] */
416 uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */
418 printf (" PCI2: 32 bit, 66 MHz, %s\n",
419 pci2_clk_sel ? "sync" : "async");
421 printf (" PCI2: disabled\n");
425 gur->devdisr |= MPC85xx_DEVDISR_PCI2; /* disable */
426 #endif /* CONFIG_PCI2 */
430 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE1_ADDR;
431 extern void fsl_pci_init(struct pci_controller *hose);
432 struct pci_controller *hose = &pcie1_hose;
433 int pcie_ep = (host_agent == 0) || (host_agent == 2 ) || (host_agent == 3);
435 int pcie_configured = io_sel >= 1;
437 if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){
438 printf ("\n PCIE connected to slot as %s (base address %x)",
439 pcie_ep ? "End Point" : "Root Complex",
442 if (pci->pme_msg_det) {
443 pci->pme_msg_det = 0xffffffff;
444 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
449 pci_set_region(hose->regions + 0,
453 PCI_REGION_MEM | PCI_REGION_MEMORY);
455 /* outbound memory */
456 pci_set_region(hose->regions + 1,
463 pci_set_region(hose->regions + 2,
469 hose->region_count = 3;
471 hose->first_busno=first_free_busno;
472 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
475 printf ("PCIE on bus %d - %d\n",hose->first_busno,hose->last_busno);
477 first_free_busno=hose->last_busno+1;
480 printf (" PCIE: disabled\n");
484 gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
489 int last_stage_init(void)
493 /* Change the resistors for the PHY */
494 /* This is needed to get the RGMII working for the 1.3+
496 if (get_board_version() == 0x13) {
497 miiphy_write(CONFIG_TSEC1_NAME,
498 TSEC1_PHY_ADDR, 29, 18);
500 miiphy_read(CONFIG_TSEC1_NAME,
501 TSEC1_PHY_ADDR, 30, &temp);
503 temp = (temp & 0xf03f);
504 temp |= 2 << 9; /* 36 ohm */
505 temp |= 2 << 6; /* 39 ohm */
507 miiphy_write(CONFIG_TSEC1_NAME,
508 TSEC1_PHY_ADDR, 30, temp);
510 miiphy_write(CONFIG_TSEC1_NAME,
511 TSEC1_PHY_ADDR, 29, 3);
513 miiphy_write(CONFIG_TSEC1_NAME,
514 TSEC1_PHY_ADDR, 30, 0x8000);
521 #if defined(CONFIG_OF_BOARD_SETUP)
523 ft_pci_setup(void *blob, bd_t *bd)
528 node = fdt_path_offset(blob, "/aliases");
532 path = fdt_getprop(blob, node, "pci0", NULL);
534 tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno;
535 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
539 path = fdt_getprop(blob, node, "pci1", NULL);
541 tmp[1] = pcie1_hose.last_busno - pcie1_hose.first_busno;
542 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);