2 * Copyright 2004, 2007, 2009-2010 Freescale Semiconductor, Inc.
4 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 #include <asm/processor.h>
29 #include <asm/immap_85xx.h>
30 #include <asm/fsl_pci.h>
31 #include <asm/fsl_ddr_sdram.h>
32 #include <asm/fsl_serdes.h>
33 #include <spd_sdram.h>
36 #include <fdt_support.h>
38 #include "../common/cadmus.h"
39 #include "../common/eeprom.h"
40 #include "../common/via.h"
42 DECLARE_GLOBAL_DATA_PTR;
44 void local_bus_init(void);
48 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
49 volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
51 /* PCI slot in USER bits CSR[6:7] by convention. */
52 uint pci_slot = get_pci_slot ();
54 uint cpu_board_rev = get_cpu_board_revision ();
56 printf ("Board: CDS Version 0x%02x, PCI Slot %d\n",
57 get_board_version (), pci_slot);
59 printf ("CPU Board Revision %d.%d (0x%04x)\n",
60 MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev),
61 MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev);
63 * Initialize local bus.
68 * Hack TSEC 3 and 4 IO voltages.
70 gur->tsec34ioovcr = 0xe7e0; /* 1110 0111 1110 0xxx */
72 ecm->eedr = 0xffffffff; /* clear ecm errors */
73 ecm->eeer = 0xffffffff; /* enable ecm errors */
78 * Initialize Local Bus
83 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
84 volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
90 get_sys_info(&sysinfo);
91 clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2;
92 lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
94 gur->lbiuiplldcr1 = 0x00078080;
96 gur->lbiuiplldcr0 = 0x7c0f1bf0;
97 } else if (clkdiv == 8) {
98 gur->lbiuiplldcr0 = 0x6c0f1bf0;
99 } else if (clkdiv == 4) {
100 gur->lbiuiplldcr0 = 0x5c0f1bf0;
103 lbc->lcrr |= 0x00030000;
105 asm("sync;isync;msync");
107 lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */
108 lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */
112 * Initialize SDRAM memory on the Local Bus.
114 void lbc_sdram_init(void)
116 #if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
119 volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
120 uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
125 print_size(CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024,
129 * Setup SDRAM Base and Option Registers
131 set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
132 set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
133 lbc->lbcr = CONFIG_SYS_LBC_LBCR;
136 lbc->lsrt = CONFIG_SYS_LBC_LSRT;
137 lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
141 * MPC8548 uses "new" 15-16 style addressing.
143 cpu_board_rev = get_cpu_board_revision();
144 lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON;
145 lsdmr_common |= LSDMR_BSMA1516;
148 * Issue PRECHARGE ALL command.
150 lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL;
153 ppcDcbf((unsigned long) sdram_addr);
157 * Issue 8 AUTO REFRESH commands.
159 for (idx = 0; idx < 8; idx++) {
160 lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH;
163 ppcDcbf((unsigned long) sdram_addr);
168 * Issue 8 MODE-set command.
170 lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW;
173 ppcDcbf((unsigned long) sdram_addr);
177 * Issue NORMAL OP command.
179 lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
182 ppcDcbf((unsigned long) sdram_addr);
183 udelay(200); /* Overkill. Must wait > 200 bus cycles */
185 #endif /* enable SDRAM init */
188 #if defined(CONFIG_PCI) || defined(CONFIG_PCI1)
189 /* For some reason the Tundra PCI bridge shows up on itself as a
190 * different device. Work around that by refusing to configure it.
192 void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { }
194 static struct pci_config_table pci_mpc85xxcds_config_table[] = {
195 {0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}},
196 {0x1106, 0x0686, PCI_ANY_ID, 1, VIA_ID, 0, mpc85xx_config_via, {0,0,0}},
197 {0x1106, 0x0571, PCI_ANY_ID, 1, VIA_ID, 1,
198 mpc85xx_config_via_usbide, {0,0,0}},
199 {0x1105, 0x3038, PCI_ANY_ID, 1, VIA_ID, 2,
200 mpc85xx_config_via_usb, {0,0,0}},
201 {0x1106, 0x3038, PCI_ANY_ID, 1, VIA_ID, 3,
202 mpc85xx_config_via_usb2, {0,0,0}},
203 {0x1106, 0x3058, PCI_ANY_ID, 1, VIA_ID, 5,
204 mpc85xx_config_via_power, {0,0,0}},
205 {0x1106, 0x3068, PCI_ANY_ID, 1, VIA_ID, 6,
206 mpc85xx_config_via_ac97, {0,0,0}},
210 static struct pci_controller pci1_hose = {
211 config_table: pci_mpc85xxcds_config_table};
212 #endif /* CONFIG_PCI */
215 static struct pci_controller pci2_hose;
216 #endif /* CONFIG_PCI2 */
218 void pci_init_board(void)
220 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
221 struct fsl_pci_info pci_info;
222 u32 devdisr, pordevsr, io_sel;
223 u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel;
224 int first_free_busno = 0;
226 devdisr = in_be32(&gur->devdisr);
227 pordevsr = in_be32(&gur->pordevsr);
228 porpllsr = in_be32(&gur->porpllsr);
229 io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
231 debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel);
234 pci_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */
235 pci_32 = pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32; /* PORDEVSR[15] */
236 pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
237 pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
239 if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
240 SET_STD_PCI_INFO(pci_info, 1);
241 set_next_law(pci_info.mem_phys,
242 law_size_bits(pci_info.mem_size), pci_info.law);
243 set_next_law(pci_info.io_phys,
244 law_size_bits(pci_info.io_size), pci_info.law);
246 pci_agent = fsl_setup_hose(&pci1_hose, pci_info.regs);
247 printf("PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
249 (pci_speed == 33333000) ? "33" :
250 (pci_speed == 66666000) ? "66" : "unknown",
251 pci_clk_sel ? "sync" : "async",
252 pci_agent ? "agent" : "host",
253 pci_arb ? "arbiter" : "external-arbiter",
256 first_free_busno = fsl_pci_init_port(&pci_info,
257 &pci1_hose, first_free_busno);
259 #ifdef CONFIG_PCIX_CHECK
260 if (!(pordevsr & MPC85xx_PORDEVSR_PCI1)) {
262 if (CONFIG_SYS_CLK_FREQ < 66000000)
263 printf("PCI-X will only work at 66 MHz\n");
265 reg16 = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ
266 | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
267 pci_hose_write_config_word(hose, bus, PCIX_COMMAND, reg16);
271 printf("PCI: disabled\n");
276 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */
281 uint pci2_clk_sel = porpllsr & 0x4000; /* PORPLLSR[17] */
282 uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */
284 printf("PCI2: 32 bit, 66 MHz, %s\n",
285 pci2_clk_sel ? "sync" : "async");
287 printf("PCI2: disabled\n");
291 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI2); /* disable */
292 #endif /* CONFIG_PCI2 */
294 fsl_pcie_init_board(first_free_busno);
297 int last_stage_init(void)
301 /* Change the resistors for the PHY */
302 /* This is needed to get the RGMII working for the 1.3+
304 if (get_board_version() == 0x13) {
305 miiphy_write(CONFIG_TSEC1_NAME,
306 TSEC1_PHY_ADDR, 29, 18);
308 miiphy_read(CONFIG_TSEC1_NAME,
309 TSEC1_PHY_ADDR, 30, &temp);
311 temp = (temp & 0xf03f);
312 temp |= 2 << 9; /* 36 ohm */
313 temp |= 2 << 6; /* 39 ohm */
315 miiphy_write(CONFIG_TSEC1_NAME,
316 TSEC1_PHY_ADDR, 30, temp);
318 miiphy_write(CONFIG_TSEC1_NAME,
319 TSEC1_PHY_ADDR, 29, 3);
321 miiphy_write(CONFIG_TSEC1_NAME,
322 TSEC1_PHY_ADDR, 30, 0x8000);
329 #if defined(CONFIG_OF_BOARD_SETUP)
330 void ft_pci_setup(void *blob, bd_t *bd)