2 * Copyright 2008, 2011 Freescale Semiconductor, Inc.
5 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
7 * SPDX-License-Identifier: GPL-2.0+
13 struct fsl_e_tlb_entry tlb_table[] = {
14 /* TLB 0 - for temp stack in cache */
15 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
16 MAS3_SX|MAS3_SW|MAS3_SR, 0,
17 0, 0, BOOKE_PAGESZ_4K, 0),
18 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
19 MAS3_SX|MAS3_SW|MAS3_SR, 0,
20 0, 0, BOOKE_PAGESZ_4K, 0),
21 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
22 MAS3_SX|MAS3_SW|MAS3_SR, 0,
23 0, 0, BOOKE_PAGESZ_4K, 0),
24 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
25 MAS3_SX|MAS3_SW|MAS3_SR, 0,
26 0, 0, BOOKE_PAGESZ_4K, 0),
31 * FLASH(cover boot page) 16M Non-cacheable, guarded
33 SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
34 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
35 0, 0, BOOKE_PAGESZ_16M, 1),
39 * CCSRBAR 1M Non-cacheable, guarded
41 SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
42 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
43 0, 1, BOOKE_PAGESZ_1M, 1),
47 * LBC SDRAM 64M Cacheable, non-guarded
49 SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE,
50 CONFIG_SYS_LBC_SDRAM_BASE_PHYS,
51 MAS3_SX|MAS3_SW|MAS3_SR, 0,
52 0, 2, BOOKE_PAGESZ_64M, 1),
56 * CADMUS registers 1M Non-cacheable, guarded
58 SET_TLB_ENTRY(1, CADMUS_BASE_ADDR, CADMUS_BASE_ADDR_PHYS,
59 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
60 0, 3, BOOKE_PAGESZ_1M, 1),
64 * PCI and PCIe MEM 1G Non-cacheable, guarded
66 SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS,
67 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
68 0, 4, BOOKE_PAGESZ_1G, 1),
72 * PCI1 IO 1M Non-cacheable, guarded
74 SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_IO_VIRT, CONFIG_SYS_PCI1_IO_PHYS,
75 MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
76 0, 5, BOOKE_PAGESZ_1M, 1),
80 * PCIe IO 1M Non-cacheable, guarded
82 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
83 MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
84 0, 6, BOOKE_PAGESZ_1M, 1),
87 int num_tlb_entries = ARRAY_SIZE(tlb_table);