2 * Copyright 2008, 2011 Freescale Semiconductor, Inc.
5 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 struct fsl_e_tlb_entry tlb_table[] = {
30 /* TLB 0 - for temp stack in cache */
31 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
32 MAS3_SX|MAS3_SW|MAS3_SR, 0,
33 0, 0, BOOKE_PAGESZ_4K, 0),
34 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
35 MAS3_SX|MAS3_SW|MAS3_SR, 0,
36 0, 0, BOOKE_PAGESZ_4K, 0),
37 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
38 MAS3_SX|MAS3_SW|MAS3_SR, 0,
39 0, 0, BOOKE_PAGESZ_4K, 0),
40 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
41 MAS3_SX|MAS3_SW|MAS3_SR, 0,
42 0, 0, BOOKE_PAGESZ_4K, 0),
45 * TLB 0: 16M Non-cacheable, guarded
46 * 0xff000000 16M FLASH
47 * Out of reset this entry is only 4K.
49 SET_TLB_ENTRY(1, CONFIG_SYS_BOOT_BLOCK, CONFIG_SYS_BOOT_BLOCK,
50 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
51 0, 0, BOOKE_PAGESZ_16M, 1),
54 * TLB 1: 1G Non-cacheable, guarded
55 * 0x80000000 1G PCI1/PCIE 8,9,a,b
57 SET_TLB_ENTRY(1, CONFIG_SYS_PCI_VIRT, CONFIG_SYS_PCI_PHYS,
58 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
59 0, 1, BOOKE_PAGESZ_1G, 1),
62 * TLB 2: 256M Non-cacheable, guarded
64 SET_TLB_ENTRY(1, CONFIG_SYS_SRIO1_MEM_VIRT, CONFIG_SYS_SRIO1_MEM_PHYS,
65 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
66 0, 2, BOOKE_PAGESZ_256M, 1),
69 * TLB 3: 256M Non-cacheable, guarded
71 SET_TLB_ENTRY(1, CONFIG_SYS_SRIO1_MEM_VIRT + 0x10000000, CONFIG_SYS_SRIO1_MEM_PHYS + 0x10000000,
72 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
73 0, 3, BOOKE_PAGESZ_256M, 1),
76 * TLB 5: 64M Non-cacheable, guarded
77 * 0xe000_0000 1M CCSRBAR
78 * 0xe200_0000 1M PCI1 IO
79 * 0xe210_0000 1M PCI2 IO
80 * 0xe300_0000 1M PCIe IO
82 SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
83 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
84 0, 5, BOOKE_PAGESZ_64M, 1),
87 * TLB 6: 64M Cacheable, non-guarded
88 * 0xf000_0000 64M LBC SDRAM
90 SET_TLB_ENTRY(1, CONFIG_SYS_LBC_CACHE_BASE, CONFIG_SYS_LBC_CACHE_BASE,
91 MAS3_SX|MAS3_SW|MAS3_SR, 0,
92 0, 6, BOOKE_PAGESZ_64M, 1),
95 * TLB 7: 64M Non-cacheable, guarded
96 * 0xf8000000 64M CADMUS registers, relocated L2SRAM
98 SET_TLB_ENTRY(1, CONFIG_SYS_LBC_NONCACHE_BASE, CONFIG_SYS_LBC_NONCACHE_BASE,
99 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
100 0, 7, BOOKE_PAGESZ_64M, 1),
103 int num_tlb_entries = ARRAY_SIZE(tlb_table);