2 * Copyright 2004-2007 Freescale Semiconductor.
3 * Copyright 2002,2003, Motorola Inc.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 #include <ppc_asm.tmpl>
26 #include <asm/cache.h>
32 * TLB0 and TLB1 Entries
34 * Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR.
35 * However, CCSRBAR is then relocated to CFG_CCSRBAR right after
36 * these TLB entries are established.
38 * The TLB entries for DDR are dynamically setup in spd_sdram()
39 * and use TLB1 Entries 8 through 15 as needed according to the
42 * MAS0: tlbsel, esel, nv
43 * MAS1: valid, iprot, tid, ts, tsize
44 * MAS2: epn, x0, x1, w, i, m, g, e
45 * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr
57 .section .bootpg, "ax"
63 * Number of TLB0 and TLB1 entries in the following table
68 #if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
70 * TLB0 4K Non-cacheable, guarded
71 * 0xff700000 4K Initial CCSRBAR mapping
73 * This ends up at a TLB0 Index==0 entry, and must not collide
74 * with other TLB0 Entries.
76 .long FSL_BOOKE_MAS0(0, 0, 0)
77 .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
78 .long FSL_BOOKE_MAS2(CFG_CCSRBAR_DEFAULT, (MAS2_I|MAS2_G))
79 .long FSL_BOOKE_MAS3(CFG_CCSRBAR_DEFAULT, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
81 #error("Update the number of table entries in tlb1_entry")
85 * TLB0 16K Cacheable, non-guarded
86 * 0xd001_0000 16K Temporary Global data for initialization
88 * Use four 4K TLB0 entries. These entries must be cacheable
89 * as they provide the bootstrap memory before the memory
90 * controler and real memory have been configured.
92 * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c,
93 * and must not collide with other TLB0 entries.
96 .long FSL_BOOKE_MAS0(0, 0, 0)
97 .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
98 .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR, 0)
99 .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
101 .long FSL_BOOKE_MAS0(0, 0, 0)
102 .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
103 .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 4 * 1024, 0)
104 .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 4 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
106 .long FSL_BOOKE_MAS0(0, 0, 0)
107 .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
108 .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 8 * 1024, 0)
109 .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 8 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
111 .long FSL_BOOKE_MAS0(0, 0, 0)
112 .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
113 .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 12 * 1024, 0)
114 .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 12 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
116 /* TLB 1 Initializations */
118 * TLBe 0: 16M Non-cacheable, guarded
119 * 0xff000000 16M FLASH (upper half)
120 * Out of reset this entry is only 4K.
122 .long FSL_BOOKE_MAS0(1, 0, 0)
123 .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)
124 .long FSL_BOOKE_MAS2(CFG_FLASH_BASE + 0x1000000, (MAS2_I|MAS2_G))
125 .long FSL_BOOKE_MAS3(CFG_FLASH_BASE + 0x1000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
128 * TLBe 1: 16M Non-cacheable, guarded
129 * 0xfe000000 16M FLASH (lower half)
131 .long FSL_BOOKE_MAS0(1, 1, 0)
132 .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)
133 .long FSL_BOOKE_MAS2(CFG_FLASH_BASE, (MAS2_I|MAS2_G))
134 .long FSL_BOOKE_MAS3(CFG_FLASH_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
137 * TLBe 2: 1G Non-cacheable, guarded
138 * 0x80000000 512M PCI1 MEM
139 * 0xa0000000 512M PCIe MEM
141 .long FSL_BOOKE_MAS0(1, 2, 0)
142 .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1G)
143 .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_BASE, (MAS2_I|MAS2_G))
144 .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
147 * TLBe 3: 64M Non-cacheable, guarded
148 * 0xe000_0000 1M CCSRBAR
149 * 0xe200_0000 8M PCI1 IO
150 * 0xe280_0000 8M PCIe IO
152 .long FSL_BOOKE_MAS0(1, 3, 0)
153 .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
154 .long FSL_BOOKE_MAS2(CFG_CCSRBAR, (MAS2_I|MAS2_G))
155 .long FSL_BOOKE_MAS3(CFG_CCSRBAR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
158 * TLBe 4: 64M Cacheable, non-guarded
159 * 0xf000_0000 64M LBC SDRAM
161 .long FSL_BOOKE_MAS0(1, 4, 0)
162 .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
163 .long FSL_BOOKE_MAS2(CFG_LBC_SDRAM_BASE, 0)
164 .long FSL_BOOKE_MAS3(CFG_LBC_SDRAM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
167 * TLBe 5: 256K Non-cacheable, guarded
168 * 0xf8000000 32K BCSR
169 * 0xf8008000 32K PIB (CS4)
170 * 0xf8010000 32K PIB (CS5)
172 .long FSL_BOOKE_MAS0(1, 5, 0)
173 .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256K)
174 .long FSL_BOOKE_MAS2(CFG_BCSR_BASE, (MAS2_I|MAS2_G))
175 .long FSL_BOOKE_MAS3(CFG_BCSR_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
181 * LAW(Local Access Window) configuration:
183 *0) 0x0000_0000 0x7fff_ffff DDR 2G
184 *1) 0x8000_0000 0x9fff_ffff PCI1 MEM 512MB
185 *2) 0xa000_0000 0xbfff_ffff PCIe MEM 512MB
186 *-) 0xe000_0000 0xe00f_ffff CCSR 1M
187 *3) 0xe200_0000 0xe27f_ffff PCI1 I/O 8M
188 *4) 0xe280_0000 0xe2ff_ffff PCIe I/O 8M
189 *5) 0xc000_0000 0xdfff_ffff SRIO 512MB
190 *6.a) 0xf000_0000 0xf3ff_ffff SDRAM 64MB
191 *6.b) 0xf800_0000 0xf800_7fff BCSR 32KB
192 *6.c) 0xf800_8000 0xf800_ffff PIB (CS4) 32KB
193 *6.d) 0xf801_0000 0xf801_7fff PIB (CS5) 32KB
194 *6.e) 0xfe00_0000 0xffff_ffff Flash 32MB
197 * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
198 * If flash is 8M at default position (last 8M), no LAW needed.
200 * The defines below are 1-off of the actual LAWAR0 usage.
201 * So LAWAR3 define uses the LAWAR4 register in the ECM.
205 #define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN)
207 #define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff)
208 #define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M))
210 #define LAWBAR2 ((CFG_PCIE1_MEM_BASE>>12) & 0xfffff)
211 #define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_512M))
213 #define LAWBAR3 ((CFG_PCI1_IO_PHYS>>12) & 0xfffff)
214 #define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_8M))
216 #define LAWBAR4 ((CFG_PCIE1_IO_PHYS>>12) & 0xfffff)
217 #define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_8M))
219 #define LAWBAR5 ((CFG_SRIO_MEM_BASE>>12) & 0xfffff)
220 #define LAWAR5 (LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M))
222 /* LBC window - maps 256M. That's SDRAM, BCSR, PIBs, and Flash */
223 #define LAWBAR6 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff)
224 #define LAWAR6 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M))
226 .section .bootpg, "ax"
233 .long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3
234 .long LAWBAR4,LAWAR4,LAWBAR5,LAWAR5,LAWBAR6,LAWAR6