2 * Copyright 2009 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0
9 #include <fsl_ddr_sdram.h>
10 #include <fsl_ddr_dimm_params.h>
12 void fsl_ddr_board_options(memctl_options_t *popts,
14 unsigned int ctrl_num)
17 * Factors to consider for clock adjust:
18 * - number of chips on bus
23 * This needs to be determined on a board-by-board basis.
27 popts->clk_adjust = 4;
30 * Factors to consider for CPO:
34 popts->cpo_override = 0xff;
37 * Factors to consider for write data delay:
47 popts->write_data_delay = 2;
50 * Enable half drive strength
52 popts->half_strength_driver_enable = 1;
54 /* Write leveling override */
56 popts->wrlvl_override = 1;
57 popts->wrlvl_sample = 0xa;
58 popts->wrlvl_start = 0x4;
60 /* Rtt and Rtt_W override */
61 popts->rtt_override = 1;
62 popts->rtt_override_value = DDR3_RTT_60_OHM;
63 popts->rtt_wr_override_value = 0; /* Rtt_WR= dynamic ODT off */