2 * Copyright 2009-2010 Freescale Semiconductor, Inc.
5 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
7 * SPDX-License-Identifier: GPL-2.0+
13 struct fsl_e_tlb_entry tlb_table[] = {
14 /* TLB 0 - for temp stack in cache */
15 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
16 MAS3_SX|MAS3_SW|MAS3_SR, 0,
17 0, 0, BOOKE_PAGESZ_4K, 0),
18 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
19 CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
20 MAS3_SX|MAS3_SW|MAS3_SR, 0,
21 0, 0, BOOKE_PAGESZ_4K, 0),
22 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
23 CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
24 MAS3_SX|MAS3_SW|MAS3_SR, 0,
25 0, 0, BOOKE_PAGESZ_4K, 0),
26 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
27 CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
28 MAS3_SX|MAS3_SW|MAS3_SR, 0,
29 0, 0, BOOKE_PAGESZ_4K, 0),
31 /* TLB 1 Initializations */
33 * TLBe 0: 64M write-through, guarded
34 * Out of reset this entry is only 4K.
35 * 0xfc000000 32MB NAND FLASH (CS3)
36 * 0xfe000000 32MB NOR FLASH (CS0)
38 #ifdef CONFIG_NAND_SPL
39 SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE,
40 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
41 0, 0, BOOKE_PAGESZ_1M, 1),
43 SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE,
44 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
45 0, 0, BOOKE_PAGESZ_64M, 1),
48 * TLBe 1: 256KB Non-cacheable, guarded
50 * 0xf8008000 32K PIB (CS4)
51 * 0xf8010000 32K PIB (CS5)
53 SET_TLB_ENTRY(1, CONFIG_SYS_BCSR_BASE, CONFIG_SYS_BCSR_BASE_PHYS,
54 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
55 0, 1, BOOKE_PAGESZ_256K, 1),
58 * TLBe 2: 256M Non-cacheable, guarded
59 * 0xa00000000 256M PCIe MEM (lower half)
61 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
62 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
63 0, 2, BOOKE_PAGESZ_256M, 1),
66 * TLBe 3: 256M Non-cacheable, guarded
67 * 0xb00000000 256M PCIe MEM (higher half)
69 SET_TLB_ENTRY(1, (CONFIG_SYS_PCIE1_MEM_VIRT + 0x10000000),
70 (CONFIG_SYS_PCIE1_MEM_PHYS + 0x10000000),
71 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
72 0, 3, BOOKE_PAGESZ_256M, 1),
75 * TLBe 4: 64M Non-cacheable, guarded
76 * 0xe000_0000 1M CCSRBAR
77 * 0xe280_0000 8M PCIe IO
79 SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
80 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
81 0, 4, BOOKE_PAGESZ_64M, 1),
83 #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
85 SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
86 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
87 0, 5, BOOKE_PAGESZ_256K, 1),
88 SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000,
89 CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000,
90 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
91 0, 6, BOOKE_PAGESZ_256K, 1),
95 int num_tlb_entries = ARRAY_SIZE(tlb_table);