2 * Copyright 2008 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * Version 2 as published by the Free Software Foundation.
12 #include <asm/fsl_ddr_sdram.h>
13 #include <asm/fsl_ddr_dimm_params.h>
15 static void get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address)
17 i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t));
20 unsigned int fsl_ddr_get_mem_data_rate(void)
22 return get_ddr_freq(0);
25 void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd,
26 unsigned int ctrl_num)
29 unsigned int i2c_address = 0;
31 for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
32 if (ctrl_num == 0 && i == 0) {
33 i2c_address = SPD_EEPROM_ADDRESS1;
35 if (ctrl_num == 1 && i == 0) {
36 i2c_address = SPD_EEPROM_ADDRESS2;
38 get_spd(&(ctrl_dimms_spd[i]), i2c_address);
44 u32 datarate_mhz_high;
50 } board_specific_parameters_t;
53 * CPO value doesn't matter if workaround for errata 111 and 134 enabled.
55 * For DDR2 DIMM, all combinations of clk_adjust and write_data_delay have been
56 * tested. For RDIMM, clk_adjust = 4 and write_data_delay = 3 is optimized for
57 * all clocks from 400MT/s to 800MT/s, verified with Kingston KVR800D2D8P6/2G.
58 * For UDIMM, clk_adjust = 8 and write_delay = 5 is optimized for all clocks
59 * from 400MT/s to 800MT/s, verified with Micron MT18HTF25672AY-800E1.
61 const board_specific_parameters_t board_specific_parameters_udimm[][20] = {
65 * lo| hi| num| clk| cpo|wrdata|2T
66 * mhz| mhz|ranks|adjst| | delay|
68 { 0, 333, 2, 8, 7, 5, 0},
69 {334, 400, 2, 8, 9, 5, 0},
70 {401, 549, 2, 8, 11, 5, 0},
71 {550, 680, 2, 8, 10, 5, 0},
72 {681, 850, 2, 8, 12, 5, 1},
73 { 0, 333, 1, 6, 7, 3, 0},
74 {334, 400, 1, 6, 9, 3, 0},
75 {401, 549, 1, 6, 11, 3, 0},
76 {550, 680, 1, 1, 10, 5, 0},
77 {681, 850, 1, 1, 12, 5, 0}
83 * lo| hi| num| clk| cpo|wrdata|2T
84 * mhz| mhz|ranks|adjst| | delay|
86 { 0, 333, 2, 8, 7, 5, 0},
87 {334, 400, 2, 8, 9, 5, 0},
88 {401, 549, 2, 8, 11, 5, 0},
89 {550, 680, 2, 8, 11, 5, 0},
90 {681, 850, 2, 8, 13, 5, 1},
91 { 0, 333, 1, 6, 7, 3, 0},
92 {334, 400, 1, 6, 9, 3, 0},
93 {401, 549, 1, 6, 11, 3, 0},
94 {550, 680, 1, 1, 11, 6, 0},
95 {681, 850, 1, 1, 13, 6, 0}
99 const board_specific_parameters_t board_specific_parameters_rdimm[][20] = {
102 * memory controller 0
103 * lo| hi| num| clk| cpo|wrdata|2T
104 * mhz| mhz|ranks|adjst| | delay|
106 { 0, 333, 2, 4, 7, 3, 0},
107 {334, 400, 2, 4, 9, 3, 0},
108 {401, 549, 2, 4, 11, 3, 0},
109 {550, 680, 2, 4, 10, 3, 0},
110 {681, 850, 2, 4, 12, 3, 1},
115 * memory controller 1
116 * lo| hi| num| clk| cpo|wrdata|2T
117 * mhz| mhz|ranks|adjst| | delay|
119 { 0, 333, 2, 4, 7, 3, 0},
120 {334, 400, 2, 4, 9, 3, 0},
121 {401, 549, 2, 4, 11, 3, 0},
122 {550, 680, 2, 4, 11, 3, 0},
123 {681, 850, 2, 4, 13, 3, 1},
127 void fsl_ddr_board_options(memctl_options_t *popts,
128 dimm_params_t *pdimm,
129 unsigned int ctrl_num)
131 const board_specific_parameters_t *pbsp;
140 if (popts->registered_dimm_en) {
141 pbsp = &(board_specific_parameters_rdimm[ctrl_num][0]);
142 num_params = sizeof(board_specific_parameters_rdimm[ctrl_num]) /
143 sizeof(board_specific_parameters_rdimm[0][0]);
145 pbsp = &(board_specific_parameters_udimm[ctrl_num][0]);
146 num_params = sizeof(board_specific_parameters_udimm[ctrl_num]) /
147 sizeof(board_specific_parameters_udimm[0][0]);
150 /* set odt_rd_cfg and odt_wr_cfg. If the there is only one dimm in
151 * that controller, set odt_wr_cfg to 4 for CS0, and 0 to CS1. If
152 * there are two dimms in the controller, set odt_rd_cfg to 3 and
153 * odt_wr_cfg to 3 for the even CS, 0 for the odd CS.
155 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
156 if (i&1) { /* odd CS */
157 popts->cs_local_opts[i].odt_rd_cfg = 0;
158 popts->cs_local_opts[i].odt_wr_cfg = 0;
159 } else { /* even CS */
160 if (CONFIG_DIMM_SLOTS_PER_CTLR == 1) {
161 popts->cs_local_opts[i].odt_rd_cfg = 0;
162 popts->cs_local_opts[i].odt_wr_cfg = 4;
163 } else if (CONFIG_DIMM_SLOTS_PER_CTLR == 2) {
164 popts->cs_local_opts[i].odt_rd_cfg = 3;
165 popts->cs_local_opts[i].odt_wr_cfg = 3;
170 /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
171 * freqency and n_banks specified in board_specific_parameters table.
173 ddr_freq = get_ddr_freq(0) / 1000000;
174 for (i = 0; i < num_params; i++) {
175 if (ddr_freq >= pbsp->datarate_mhz_low &&
176 ddr_freq <= pbsp->datarate_mhz_high &&
177 pdimm->n_ranks == pbsp->n_ranks) {
178 popts->clk_adjust = pbsp->clk_adjust;
179 popts->cpo_override = pbsp->cpo;
180 popts->write_data_delay = pbsp->write_data_delay;
181 popts->twoT_en = pbsp->force_2T;
189 printf("Warning: board specific timing not found!\n");
192 * Factors to consider for half-strength driver enable:
193 * - number of DIMMs installed
195 popts->half_strength_driver_enable = 0;