git.sur5r.net Git - u-boot/blob - board/freescale/mpc8572ds/tlb.c

   1 /*
   2  * Copyright 2008 Freescale Semiconductor, Inc.
   3  *
   4  * (C) Copyright 2000
   5  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   6  *
   7  * See file CREDITS for list of people who contributed to this
   8  * project.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 of
  13  * the License, or (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23  * MA 02111-1307 USA
  24  */
  25
  26 #include <common.h>
  27 #include <asm/mmu.h>
  28
  29 struct fsl_e_tlb_entry tlb_table[] = {
  30         /* TLB 0 - for temp stack in cache */
  31         SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
  32                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
  33                       0, 0, BOOKE_PAGESZ_4K, 0),
  34         SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
  35                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
  36                       0, 0, BOOKE_PAGESZ_4K, 0),
  37         SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
  38                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
  39                       0, 0, BOOKE_PAGESZ_4K, 0),
  40         SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
  41                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
  42                       0, 0, BOOKE_PAGESZ_4K, 0),
  43
  44         SET_TLB_ENTRY(0, PIXIS_BASE, PIXIS_BASE,
  45                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  46                       0, 0, BOOKE_PAGESZ_4K, 0),
  47
  48         /* TLB 1 */
  49         /* *I*** - Covers boot page */
  50         SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
  51                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I,
  52                       0, 0, BOOKE_PAGESZ_4K, 1),
  53
  54         /* *I*G* - CCSRBAR */
  55         SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
  56                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  57                       0, 1, BOOKE_PAGESZ_1M, 1),
  58
  59         /* W**G* - Flash/promjet, localbus */
  60         /* This will be changed to *I*G* after relocation to RAM. */
  61         SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE,
  62                       MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
  63                       0, 2, BOOKE_PAGESZ_256M, 1),
  64
  65         /* *I*G* - PCI */
  66         SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_PHYS, CONFIG_SYS_PCIE3_MEM_PHYS,
  67                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  68                       0, 3, BOOKE_PAGESZ_1G, 1),
  69
  70         /* *I*G* - PCI */
  71         SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_PHYS + 0x40000000, CONFIG_SYS_PCIE3_MEM_PHYS + 0x40000000,
  72                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  73                       0, 4, BOOKE_PAGESZ_256M, 1),
  74
  75         SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_PHYS + 0x50000000, CONFIG_SYS_PCIE3_MEM_PHYS + 0x50000000,
  76                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  77                       0, 5, BOOKE_PAGESZ_256M, 1),
  78
  79         /* *I*G* - PCI I/O */
  80         SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_IO_PHYS, CONFIG_SYS_PCIE3_IO_PHYS,
  81                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  82                       0, 6, BOOKE_PAGESZ_256K, 1),
  83
  84         /* *I*G - NAND */
  85         SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
  86                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  87                       0, 7, BOOKE_PAGESZ_1M, 1),
  88
  89 };
  90
  91 int num_tlb_entries = ARRAY_SIZE(tlb_table);