2 * Copyright 2007 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/processor.h>
27 #include <asm/immap_86xx.h>
28 #include <asm/immap_fsl_pci.h>
32 #include <fdt_support.h>
33 #include <spd_sdram.h>
35 #include "../common/pixis.h"
37 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
38 extern void ddr_enable_ecc(unsigned int dram_size);
41 void sdram_init(void);
42 long int fixed_sdram(void);
43 void mpc8610hpcd_diu_init(void);
46 /* called before any console output */
47 int board_early_init_f(void)
49 volatile immap_t *immap = (immap_t *)CFG_IMMR;
50 volatile ccsr_gur_t *gur = &immap->im_gur;
52 gur->gpiocr |= 0x88aa5500; /* DIU16, IR1, UART0, UART2 */
61 /*Do not use 8259PIC*/
62 tmp_val = in8(PIXIS_BASE + PIXIS_BRDCFG0);
63 out8(PIXIS_BASE + PIXIS_BRDCFG0, tmp_val | 0x80);
65 /*For FPGA V7 or higher, set the IRQMAPSEL to 0 to use MAP0 interrupt*/
66 version = in8(PIXIS_BASE + PIXIS_PVER);
68 tmp_val = in8(PIXIS_BASE + PIXIS_BRDCFG0);
69 out8(PIXIS_BASE + PIXIS_BRDCFG0, tmp_val & 0xbf);
72 /* Using this for DIU init before the driver in linux takes over
73 * Enable the TFP410 Encoder (I2C address 0x38)
77 i2c_write(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
78 /* Verify if enabled */
80 i2c_read(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
81 debug("DVI Encoder Read: 0x%02lx\n",tmp_val);
84 i2c_write(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
85 /* Verify if enabled */
87 i2c_read(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
88 debug("DVI Encoder Read: 0x%02lx\n",tmp_val);
90 #ifdef CONFIG_FSL_DIU_FB
91 mpc8610hpcd_diu_init();
99 volatile immap_t *immap = (immap_t *)CFG_IMMR;
100 volatile ccsr_local_mcm_t *mcm = &immap->im_local_mcm;
102 printf ("Board: MPC8610HPCD, System ID: 0x%02lx, "
103 "System Version: 0x%02lx, FPGA Version: 0x%02lx\n",
104 in8(PIXIS_BASE + PIXIS_ID), in8(PIXIS_BASE + PIXIS_VER),
105 in8(PIXIS_BASE + PIXIS_PVER));
107 mcm->abcr |= 0x00010000; /* 0 */
108 mcm->hpmr3 = 0x80000008; /* 4c */
120 initdram(int board_type)
124 #if defined(CONFIG_SPD_EEPROM)
125 dram_size = spd_sdram();
127 dram_size = fixed_sdram();
130 #if defined(CFG_RAMBOOT)
135 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
137 * Initialize and enable DDR ECC.
139 ddr_enable_ecc(dram_size);
147 #if !defined(CONFIG_SPD_EEPROM)
149 * Fixed sdram init -- doesn't use serial presence detect.
152 long int fixed_sdram(void)
154 #if !defined(CFG_RAMBOOT)
155 volatile immap_t *immap = (immap_t *)CFG_IMMR;
156 volatile ccsr_ddr_t *ddr = &immap->im_ddr1;
159 ddr->cs0_bnds = 0x0000001f;
160 ddr->cs0_config = 0x80010202;
162 ddr->timing_cfg_3 = 0x00000000;
163 ddr->timing_cfg_0 = 0x00260802;
164 ddr->timing_cfg_1 = 0x3935d322;
165 ddr->timing_cfg_2 = 0x14904cc8;
166 ddr->sdram_mode_1 = 0x00480432;
167 ddr->sdram_mode_2 = 0x00000000;
168 ddr->sdram_interval = 0x06180fff; /* 0x06180100; */
169 ddr->sdram_data_init = 0xDEADBEEF;
170 ddr->sdram_clk_cntl = 0x03800000;
171 ddr->sdram_cfg_2 = 0x04400010;
173 #if defined(CONFIG_DDR_ECC)
174 ddr->err_int_en = 0x0000000d;
175 ddr->err_disable = 0x00000000;
176 ddr->err_sbe = 0x00010000;
182 ddr->sdram_cfg_1 = 0xc3000000; /* 0xe3008000;*/
185 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
187 debug("DDR - 1st controller: memory initializing\n");
189 * Poll until memory is initialized.
190 * 512 Meg at 400 might hit this 200 times or so.
192 while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0)
195 debug("DDR: memory initialized\n\n");
200 return 512 * 1024 * 1024;
202 return CFG_SDRAM_SIZE * 1024 * 1024;
207 #if defined(CONFIG_PCI)
209 * Initialize PCI Devices, report devices found.
212 #ifndef CONFIG_PCI_PNP
213 static struct pci_config_table pci_fsl86xxads_config_table[] = {
214 {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
215 PCI_IDSEL_NUMBER, PCI_ANY_ID,
216 pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
218 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER} },
224 static struct pci_controller pci1_hose = {
225 #ifndef CONFIG_PCI_PNP
226 config_table:pci_mpc86xxcts_config_table
229 #endif /* CONFIG_PCI */
232 static struct pci_controller pcie1_hose;
236 static struct pci_controller pcie2_hose;
239 int first_free_busno = 0;
241 void pci_init_board(void)
243 volatile immap_t *immap = (immap_t *) CFG_CCSRBAR;
244 volatile ccsr_gur_t *gur = &immap->im_gur;
245 uint devdisr = gur->devdisr;
246 uint io_sel = (gur->pordevsr & MPC8610_PORDEVSR_IO_SEL)
247 >> MPC8610_PORDEVSR_IO_SEL_SHIFT;
248 uint host_agent = (gur->porbmsr & MPC8610_PORBMSR_HA)
249 >> MPC8610_PORBMSR_HA_SHIFT;
251 printf( " pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n",
252 devdisr, io_sel, host_agent);
256 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE1_ADDR;
257 extern void fsl_pci_init(struct pci_controller *hose);
258 struct pci_controller *hose = &pcie1_hose;
259 int pcie_configured = (io_sel == 1) || (io_sel == 4);
260 int pcie_ep = (host_agent == 0) || (host_agent == 2) ||
263 if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIE1)) {
264 printf(" PCIe 1 connected to Uli as %s (base address %x)\n",
265 pcie_ep ? "End Point" : "Root Complex",
267 if (pci->pme_msg_det)
268 pci->pme_msg_det = 0xffffffff;
271 pci_set_region(hose->regions + 0,
275 PCI_REGION_MEM | PCI_REGION_MEMORY);
277 /* outbound memory */
278 pci_set_region(hose->regions + 1,
285 pci_set_region(hose->regions + 2,
291 hose->region_count = 3;
293 hose->first_busno = first_free_busno;
294 pci_setup_indirect(hose, (int)&pci->cfg_addr,
295 (int)&pci->cfg_data);
299 first_free_busno = hose->last_busno + 1;
300 printf(" PCI-Express 1 on bus %02x - %02x\n",
301 hose->first_busno, hose->last_busno);
304 puts(" PCI-Express 1: Disabled\n");
307 puts("PCI-Express 1: Disabled\n");
308 #endif /* CONFIG_PCIE1 */
313 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE2_ADDR;
314 extern void fsl_pci_init(struct pci_controller *hose);
315 struct pci_controller *hose = &pcie2_hose;
317 int pcie_configured = (io_sel == 0) || (io_sel == 4);
318 int pcie_ep = (host_agent == 0) || (host_agent == 1) ||
321 if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIE2)) {
322 printf(" PCI-Express 2 connected to slot as %s" \
323 " (base address %x)\n",
324 pcie_ep ? "End Point" : "Root Complex",
326 if (pci->pme_msg_det)
327 pci->pme_msg_det = 0xffffffff;
330 pci_set_region(hose->regions + 0,
334 PCI_REGION_MEM | PCI_REGION_MEMORY);
336 /* outbound memory */
337 pci_set_region(hose->regions + 1,
344 pci_set_region(hose->regions + 2,
350 hose->region_count = 3;
352 hose->first_busno = first_free_busno;
353 pci_setup_indirect(hose, (int)&pci->cfg_addr,
354 (int)&pci->cfg_data);
358 first_free_busno = hose->last_busno + 1;
359 printf(" PCI-Express 2 on bus %02x - %02x\n",
360 hose->first_busno, hose->last_busno);
362 puts(" PCI-Express 2: Disabled\n");
365 puts("PCI-Express 2: Disabled\n");
366 #endif /* CONFIG_PCIE2 */
371 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR;
372 extern void fsl_pci_init(struct pci_controller *hose);
373 struct pci_controller *hose = &pci1_hose;
374 int pci_agent = (host_agent >= 4) && (host_agent <= 6);
376 if ( !(devdisr & MPC86xx_DEVDISR_PCI1)) {
377 printf(" PCI connected to PCI slots as %s" \
378 " (base address %x)\n",
379 pci_agent ? "Agent" : "Host",
383 pci_set_region(hose->regions + 0,
387 PCI_REGION_MEM | PCI_REGION_MEMORY);
389 /* outbound memory */
390 pci_set_region(hose->regions + 1,
397 pci_set_region(hose->regions + 2,
403 hose->region_count = 3;
405 hose->first_busno = first_free_busno;
406 pci_setup_indirect(hose, (int) &pci->cfg_addr,
407 (int) &pci->cfg_data);
411 first_free_busno = hose->last_busno + 1;
412 printf(" PCI on bus %02x - %02x\n",
413 hose->first_busno, hose->last_busno);
417 puts(" PCI: Disabled\n");
419 #endif /* CONFIG_PCI1 */
422 #if defined(CONFIG_OF_BOARD_SETUP)
424 ft_board_setup(void *blob, bd_t *bd)
429 do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
430 "timebase-frequency", bd->bi_busfreq / 4, 1);
431 do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
432 "bus-frequency", bd->bi_busfreq, 1);
433 do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
434 "clock-frequency", bd->bi_intfreq, 1);
435 do_fixup_by_prop_u32(blob, "device_type", "soc", 4,
436 "bus-frequency", bd->bi_busfreq, 1);
438 do_fixup_by_compat_u32(blob, "ns16550",
439 "clock-frequency", bd->bi_busfreq, 1);
441 fdt_fixup_memory(blob, bd->bi_memstart, bd->bi_memsize);
444 node = fdt_path_offset(blob, "/aliases");
449 path = fdt_getprop(blob, node, "pci0", NULL);
451 tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno;
452 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
457 path = fdt_getprop(blob, node, "pci1", NULL);
459 tmp[1] = pcie1_hose.last_busno
460 - pcie1_hose.first_busno;
461 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
465 path = fdt_getprop(blob, node, "pci2", NULL);
467 tmp[1] = pcie2_hose.last_busno
468 - pcie2_hose.first_busno;
469 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
478 * Reads the FPGA on board for CONFIG_SYS_CLK_FREQ
482 get_board_sys_clk(ulong dummy)
488 a = PIXIS_BASE + PIXIS_SPD;