2 * Copyright 2007,2009-2010 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/processor.h>
27 #include <asm/immap_86xx.h>
28 #include <asm/fsl_pci.h>
29 #include <asm/fsl_ddr_sdram.h>
30 #include <asm/fsl_serdes.h>
34 #include <fdt_support.h>
35 #include <spd_sdram.h>
38 void sdram_init(void);
39 phys_size_t fixed_sdram(void);
40 int mpc8610hpcd_diu_init(void);
43 /* called before any console output */
44 int board_early_init_f(void)
46 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
47 volatile ccsr_gur_t *gur = &immap->im_gur;
49 gur->gpiocr |= 0x88aa5500; /* DIU16, IR1, UART0, UART2 */
57 u8 *pixis_base = (u8 *)PIXIS_BASE;
59 /*Do not use 8259PIC*/
60 tmp_val = in_8(pixis_base + PIXIS_BRDCFG0);
61 out_8(pixis_base + PIXIS_BRDCFG0, tmp_val | 0x80);
63 /*For FPGA V7 or higher, set the IRQMAPSEL to 0 to use MAP0 interrupt*/
64 version = in_8(pixis_base + PIXIS_PVER);
66 tmp_val = in_8(pixis_base + PIXIS_BRDCFG0);
67 out_8(pixis_base + PIXIS_BRDCFG0, tmp_val & 0xbf);
70 /* Using this for DIU init before the driver in linux takes over
71 * Enable the TFP410 Encoder (I2C address 0x38)
75 i2c_write(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
76 /* Verify if enabled */
78 i2c_read(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
79 debug("DVI Encoder Read: 0x%02lx\n",tmp_val);
82 i2c_write(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
83 /* Verify if enabled */
85 i2c_read(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
86 debug("DVI Encoder Read: 0x%02lx\n",tmp_val);
93 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
94 volatile ccsr_local_mcm_t *mcm = &immap->im_local_mcm;
95 u8 *pixis_base = (u8 *)PIXIS_BASE;
97 printf ("Board: MPC8610HPCD, System ID: 0x%02x, "
98 "System Version: 0x%02x, FPGA Version: 0x%02x\n",
99 in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
100 in_8(pixis_base + PIXIS_PVER));
102 mcm->abcr |= 0x00010000; /* 0 */
103 mcm->hpmr3 = 0x80000008; /* 4c */
115 initdram(int board_type)
117 phys_size_t dram_size = 0;
119 #if defined(CONFIG_SPD_EEPROM)
120 dram_size = fsl_ddr_sdram();
122 dram_size = fixed_sdram();
125 setup_ddr_bat(dram_size);
132 #if !defined(CONFIG_SPD_EEPROM)
134 * Fixed sdram init -- doesn't use serial presence detect.
137 phys_size_t fixed_sdram(void)
139 #if !defined(CONFIG_SYS_RAMBOOT)
140 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
141 volatile ccsr_ddr_t *ddr = &immap->im_ddr1;
144 ddr->cs0_bnds = 0x0000001f;
145 ddr->cs0_config = 0x80010202;
147 ddr->timing_cfg_3 = 0x00000000;
148 ddr->timing_cfg_0 = 0x00260802;
149 ddr->timing_cfg_1 = 0x3935d322;
150 ddr->timing_cfg_2 = 0x14904cc8;
151 ddr->sdram_mode = 0x00480432;
152 ddr->sdram_mode_2 = 0x00000000;
153 ddr->sdram_interval = 0x06180fff; /* 0x06180100; */
154 ddr->sdram_data_init = 0xDEADBEEF;
155 ddr->sdram_clk_cntl = 0x03800000;
156 ddr->sdram_cfg_2 = 0x04400010;
158 #if defined(CONFIG_DDR_ECC)
159 ddr->err_int_en = 0x0000000d;
160 ddr->err_disable = 0x00000000;
161 ddr->err_sbe = 0x00010000;
167 ddr->sdram_cfg = 0xc3000000; /* 0xe3008000;*/
170 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
172 debug("DDR - 1st controller: memory initializing\n");
174 * Poll until memory is initialized.
175 * 512 Meg at 400 might hit this 200 times or so.
177 while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0)
180 debug("DDR: memory initialized\n\n");
185 return 512 * 1024 * 1024;
187 return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
192 #if defined(CONFIG_PCI)
194 * Initialize PCI Devices, report devices found.
197 #ifndef CONFIG_PCI_PNP
198 static struct pci_config_table pci_fsl86xxads_config_table[] = {
199 {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
200 PCI_IDSEL_NUMBER, PCI_ANY_ID,
201 pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
203 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER} },
209 static struct pci_controller pci1_hose = {
210 #ifndef CONFIG_PCI_PNP
211 config_table:pci_mpc86xxcts_config_table
214 #endif /* CONFIG_PCI */
217 static struct pci_controller pcie1_hose;
221 static struct pci_controller pcie2_hose;
224 void pci_init_board(void)
226 volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR;
227 volatile ccsr_gur_t *gur = &immap->im_gur;
228 struct fsl_pci_info pci_info[3];
229 u32 devdisr, pordevsr;
230 int first_free_busno = 0;
233 int pci_agent, pcie_ep, pcie_configured;
235 devdisr = in_be32(&gur->devdisr);
236 pordevsr = in_be32(&gur->pordevsr);
239 pcie_configured = is_serdes_configured(PCIE1);
241 if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIE1)){
242 SET_STD_PCIE_INFO(pci_info[num], 1);
243 pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
244 printf("PCIE1: connected to ULI as %s (base addr %lx)\n",
245 pcie_ep ? "Endpoint" : "Root Complex",
248 first_free_busno = fsl_pci_init_port(&pci_info[num++],
249 &pcie1_hose, first_free_busno);
251 printf("PCIE1: disabled\n");
256 setbits_be32(&gur->devdisr, MPC86xx_DEVDISR_PCIE1); /* disable */
260 pcie_configured = is_serdes_configured(PCIE2);
262 if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIE2)){
263 SET_STD_PCIE_INFO(pci_info[num], 2);
264 pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
265 printf("PCIE2: connected to Slot as %s (base addr %lx)\n",
266 pcie_ep ? "Endpoint" : "Root Complex",
268 first_free_busno = fsl_pci_init_port(&pci_info[num++],
269 &pcie2_hose, first_free_busno);
271 printf("PCIE2: disabled\n");
276 setbits_be32(&gur->devdisr, MPC86xx_DEVDISR_PCIE2); /* disable */
280 if (!(devdisr & MPC86xx_DEVDISR_PCI1)) {
281 SET_STD_PCI_INFO(pci_info[num], 1);
282 pci_agent = fsl_setup_hose(&pci1_hose, pci_info[num].regs);
283 printf("PCI: connected to PCI slots as %s" \
284 " (base address %lx)\n",
285 pci_agent ? "Agent" : "Host",
287 first_free_busno = fsl_pci_init_port(&pci_info[num++],
288 &pci1_hose, first_free_busno);
290 printf("PCI: disabled\n");
295 setbits_be32(&gur->devdisr, MPC86xx_DEVDISR_PCI1); /* disable */
299 #if defined(CONFIG_OF_BOARD_SETUP)
301 ft_board_setup(void *blob, bd_t *bd)
303 ft_cpu_setup(blob, bd);
311 * Reads the FPGA on board for CONFIG_SYS_CLK_FREQ
315 get_board_sys_clk(ulong dummy)
319 u8 *pixis_base = (u8 *)PIXIS_BASE;
321 i = in_8(pixis_base + PIXIS_SPD);
354 int board_eth_init(bd_t *bis)
356 return pci_eth_init(bis);
359 void board_reset(void)
361 u8 *pixis_base = (u8 *)PIXIS_BASE;
363 out_8(pixis_base + PIXIS_RST, 0);