2 * Copyright 2007 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/processor.h>
27 #include <asm/immap_86xx.h>
28 #include <asm/immap_fsl_pci.h>
29 #include <asm/fsl_ddr_sdram.h>
33 #include <fdt_support.h>
34 #include <spd_sdram.h>
36 #include "../common/pixis.h"
38 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
39 extern void ddr_enable_ecc(unsigned int dram_size);
42 void sdram_init(void);
43 long int fixed_sdram(void);
44 void mpc8610hpcd_diu_init(void);
47 /* called before any console output */
48 int board_early_init_f(void)
50 volatile immap_t *immap = (immap_t *)CFG_IMMR;
51 volatile ccsr_gur_t *gur = &immap->im_gur;
53 gur->gpiocr |= 0x88aa5500; /* DIU16, IR1, UART0, UART2 */
62 /*Do not use 8259PIC*/
63 tmp_val = in8(PIXIS_BASE + PIXIS_BRDCFG0);
64 out8(PIXIS_BASE + PIXIS_BRDCFG0, tmp_val | 0x80);
66 /*For FPGA V7 or higher, set the IRQMAPSEL to 0 to use MAP0 interrupt*/
67 version = in8(PIXIS_BASE + PIXIS_PVER);
69 tmp_val = in8(PIXIS_BASE + PIXIS_BRDCFG0);
70 out8(PIXIS_BASE + PIXIS_BRDCFG0, tmp_val & 0xbf);
73 /* Using this for DIU init before the driver in linux takes over
74 * Enable the TFP410 Encoder (I2C address 0x38)
78 i2c_write(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
79 /* Verify if enabled */
81 i2c_read(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
82 debug("DVI Encoder Read: 0x%02lx\n",tmp_val);
85 i2c_write(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
86 /* Verify if enabled */
88 i2c_read(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
89 debug("DVI Encoder Read: 0x%02lx\n",tmp_val);
91 #ifdef CONFIG_FSL_DIU_FB
92 mpc8610hpcd_diu_init();
100 volatile immap_t *immap = (immap_t *)CFG_IMMR;
101 volatile ccsr_local_mcm_t *mcm = &immap->im_local_mcm;
103 printf ("Board: MPC8610HPCD, System ID: 0x%02x, "
104 "System Version: 0x%02x, FPGA Version: 0x%02x\n",
105 in8(PIXIS_BASE + PIXIS_ID), in8(PIXIS_BASE + PIXIS_VER),
106 in8(PIXIS_BASE + PIXIS_PVER));
108 mcm->abcr |= 0x00010000; /* 0 */
109 mcm->hpmr3 = 0x80000008; /* 4c */
121 initdram(int board_type)
125 #if defined(CONFIG_SPD_EEPROM)
126 dram_size = fsl_ddr_sdram();
128 dram_size = fixed_sdram();
131 #if defined(CFG_RAMBOOT)
136 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
138 * Initialize and enable DDR ECC.
140 ddr_enable_ecc(dram_size);
148 #if !defined(CONFIG_SPD_EEPROM)
150 * Fixed sdram init -- doesn't use serial presence detect.
153 long int fixed_sdram(void)
155 #if !defined(CFG_RAMBOOT)
156 volatile immap_t *immap = (immap_t *)CFG_IMMR;
157 volatile ccsr_ddr_t *ddr = &immap->im_ddr1;
160 ddr->cs0_bnds = 0x0000001f;
161 ddr->cs0_config = 0x80010202;
163 ddr->timing_cfg_3 = 0x00000000;
164 ddr->timing_cfg_0 = 0x00260802;
165 ddr->timing_cfg_1 = 0x3935d322;
166 ddr->timing_cfg_2 = 0x14904cc8;
167 ddr->sdram_mode_1 = 0x00480432;
168 ddr->sdram_mode_2 = 0x00000000;
169 ddr->sdram_interval = 0x06180fff; /* 0x06180100; */
170 ddr->sdram_data_init = 0xDEADBEEF;
171 ddr->sdram_clk_cntl = 0x03800000;
172 ddr->sdram_cfg_2 = 0x04400010;
174 #if defined(CONFIG_DDR_ECC)
175 ddr->err_int_en = 0x0000000d;
176 ddr->err_disable = 0x00000000;
177 ddr->err_sbe = 0x00010000;
183 ddr->sdram_cfg_1 = 0xc3000000; /* 0xe3008000;*/
186 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
188 debug("DDR - 1st controller: memory initializing\n");
190 * Poll until memory is initialized.
191 * 512 Meg at 400 might hit this 200 times or so.
193 while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0)
196 debug("DDR: memory initialized\n\n");
201 return 512 * 1024 * 1024;
203 return CFG_SDRAM_SIZE * 1024 * 1024;
208 #if defined(CONFIG_PCI)
210 * Initialize PCI Devices, report devices found.
213 #ifndef CONFIG_PCI_PNP
214 static struct pci_config_table pci_fsl86xxads_config_table[] = {
215 {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
216 PCI_IDSEL_NUMBER, PCI_ANY_ID,
217 pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
219 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER} },
225 static struct pci_controller pci1_hose = {
226 #ifndef CONFIG_PCI_PNP
227 config_table:pci_mpc86xxcts_config_table
230 #endif /* CONFIG_PCI */
233 static struct pci_controller pcie1_hose;
237 static struct pci_controller pcie2_hose;
240 int first_free_busno = 0;
242 void pci_init_board(void)
244 volatile immap_t *immap = (immap_t *) CFG_CCSRBAR;
245 volatile ccsr_gur_t *gur = &immap->im_gur;
246 uint devdisr = gur->devdisr;
247 uint io_sel = (gur->pordevsr & MPC8610_PORDEVSR_IO_SEL)
248 >> MPC8610_PORDEVSR_IO_SEL_SHIFT;
249 uint host_agent = (gur->porbmsr & MPC8610_PORBMSR_HA)
250 >> MPC8610_PORBMSR_HA_SHIFT;
252 printf( " pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n",
253 devdisr, io_sel, host_agent);
257 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE1_ADDR;
258 extern void fsl_pci_init(struct pci_controller *hose);
259 struct pci_controller *hose = &pcie1_hose;
260 int pcie_configured = (io_sel == 1) || (io_sel == 4);
261 int pcie_ep = (host_agent == 0) || (host_agent == 2) ||
264 if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIE1)) {
265 printf(" PCIe 1 connected to Uli as %s (base address %x)\n",
266 pcie_ep ? "End Point" : "Root Complex",
268 if (pci->pme_msg_det)
269 pci->pme_msg_det = 0xffffffff;
272 pci_set_region(hose->regions + 0,
276 PCI_REGION_MEM | PCI_REGION_MEMORY);
278 /* outbound memory */
279 pci_set_region(hose->regions + 1,
286 pci_set_region(hose->regions + 2,
292 hose->region_count = 3;
294 hose->first_busno = first_free_busno;
295 pci_setup_indirect(hose, (int)&pci->cfg_addr,
296 (int)&pci->cfg_data);
300 first_free_busno = hose->last_busno + 1;
301 printf(" PCI-Express 1 on bus %02x - %02x\n",
302 hose->first_busno, hose->last_busno);
305 puts(" PCI-Express 1: Disabled\n");
308 puts("PCI-Express 1: Disabled\n");
309 #endif /* CONFIG_PCIE1 */
314 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE2_ADDR;
315 extern void fsl_pci_init(struct pci_controller *hose);
316 struct pci_controller *hose = &pcie2_hose;
318 int pcie_configured = (io_sel == 0) || (io_sel == 4);
319 int pcie_ep = (host_agent == 0) || (host_agent == 1) ||
322 if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIE2)) {
323 printf(" PCI-Express 2 connected to slot as %s" \
324 " (base address %x)\n",
325 pcie_ep ? "End Point" : "Root Complex",
327 if (pci->pme_msg_det)
328 pci->pme_msg_det = 0xffffffff;
331 pci_set_region(hose->regions + 0,
335 PCI_REGION_MEM | PCI_REGION_MEMORY);
337 /* outbound memory */
338 pci_set_region(hose->regions + 1,
345 pci_set_region(hose->regions + 2,
351 hose->region_count = 3;
353 hose->first_busno = first_free_busno;
354 pci_setup_indirect(hose, (int)&pci->cfg_addr,
355 (int)&pci->cfg_data);
359 first_free_busno = hose->last_busno + 1;
360 printf(" PCI-Express 2 on bus %02x - %02x\n",
361 hose->first_busno, hose->last_busno);
363 puts(" PCI-Express 2: Disabled\n");
366 puts("PCI-Express 2: Disabled\n");
367 #endif /* CONFIG_PCIE2 */
372 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR;
373 extern void fsl_pci_init(struct pci_controller *hose);
374 struct pci_controller *hose = &pci1_hose;
375 int pci_agent = (host_agent >= 4) && (host_agent <= 6);
377 if ( !(devdisr & MPC86xx_DEVDISR_PCI1)) {
378 printf(" PCI connected to PCI slots as %s" \
379 " (base address %x)\n",
380 pci_agent ? "Agent" : "Host",
384 pci_set_region(hose->regions + 0,
388 PCI_REGION_MEM | PCI_REGION_MEMORY);
390 /* outbound memory */
391 pci_set_region(hose->regions + 1,
398 pci_set_region(hose->regions + 2,
404 hose->region_count = 3;
406 hose->first_busno = first_free_busno;
407 pci_setup_indirect(hose, (int) &pci->cfg_addr,
408 (int) &pci->cfg_data);
412 first_free_busno = hose->last_busno + 1;
413 printf(" PCI on bus %02x - %02x\n",
414 hose->first_busno, hose->last_busno);
418 puts(" PCI: Disabled\n");
420 #endif /* CONFIG_PCI1 */
423 #if defined(CONFIG_OF_BOARD_SETUP)
425 ft_board_setup(void *blob, bd_t *bd)
430 do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
431 "timebase-frequency", bd->bi_busfreq / 4, 1);
432 do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
433 "bus-frequency", bd->bi_busfreq, 1);
434 do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
435 "clock-frequency", bd->bi_intfreq, 1);
436 do_fixup_by_prop_u32(blob, "device_type", "soc", 4,
437 "bus-frequency", bd->bi_busfreq, 1);
439 do_fixup_by_compat_u32(blob, "ns16550",
440 "clock-frequency", bd->bi_busfreq, 1);
442 fdt_fixup_memory(blob, bd->bi_memstart, bd->bi_memsize);
445 node = fdt_path_offset(blob, "/aliases");
450 path = fdt_getprop(blob, node, "pci0", NULL);
452 tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno;
453 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
458 path = fdt_getprop(blob, node, "pci1", NULL);
460 tmp[1] = pcie1_hose.last_busno
461 - pcie1_hose.first_busno;
462 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
466 path = fdt_getprop(blob, node, "pci2", NULL);
468 tmp[1] = pcie2_hose.last_busno
469 - pcie2_hose.first_busno;
470 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
479 * Reads the FPGA on board for CONFIG_SYS_CLK_FREQ
483 get_board_sys_clk(ulong dummy)
489 a = PIXIS_BASE + PIXIS_SPD;
523 extern int uli526x_initialize(bd_t *);
525 int board_eth_init(bd_t *bis)
527 #if defined(CONFIG_ULI526)
528 uli526x_initialize(bis);