2 * Copyright 2006, 2007 Freescale Semiconductor.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <asm/processor.h>
26 #include <asm/immap_86xx.h>
27 #include <asm/immap_fsl_pci.h>
31 #include <fdt_support.h>
33 #include "../common/pixis.h"
35 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
36 extern void ddr_enable_ecc(unsigned int dram_size);
39 #if defined(CONFIG_SPD_EEPROM)
40 #include "spd_sdram.h"
43 void sdram_init(void);
44 long int fixed_sdram(void);
47 int board_early_init_f(void)
54 puts("Board: MPC8641HPCN\n");
61 initdram(int board_type)
65 #if defined(CONFIG_SPD_EEPROM)
66 dram_size = spd_sdram();
68 dram_size = fixed_sdram();
71 #if defined(CFG_RAMBOOT)
76 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
78 * Initialize and enable DDR ECC.
80 ddr_enable_ecc(dram_size);
88 #if defined(CFG_DRAM_TEST)
92 uint *pstart = (uint *) CFG_MEMTEST_START;
93 uint *pend = (uint *) CFG_MEMTEST_END;
96 puts("SDRAM test phase 1:\n");
97 for (p = pstart; p < pend; p++)
100 for (p = pstart; p < pend; p++) {
101 if (*p != 0xaaaaaaaa) {
102 printf("SDRAM test fails at: %08x\n", (uint) p);
107 puts("SDRAM test phase 2:\n");
108 for (p = pstart; p < pend; p++)
111 for (p = pstart; p < pend; p++) {
112 if (*p != 0x55555555) {
113 printf("SDRAM test fails at: %08x\n", (uint) p);
118 puts("SDRAM test passed.\n");
124 #if !defined(CONFIG_SPD_EEPROM)
126 * Fixed sdram init -- doesn't use serial presence detect.
131 #if !defined(CFG_RAMBOOT)
132 volatile immap_t *immap = (immap_t *) CFG_IMMR;
133 volatile ccsr_ddr_t *ddr = &immap->im_ddr1;
135 ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
136 ddr->cs0_config = CFG_DDR_CS0_CONFIG;
137 ddr->ext_refrec = CFG_DDR_EXT_REFRESH;
138 ddr->timing_cfg_0 = CFG_DDR_TIMING_0;
139 ddr->timing_cfg_1 = CFG_DDR_TIMING_1;
140 ddr->timing_cfg_2 = CFG_DDR_TIMING_2;
141 ddr->sdram_mode_1 = CFG_DDR_MODE_1;
142 ddr->sdram_mode_2 = CFG_DDR_MODE_2;
143 ddr->sdram_interval = CFG_DDR_INTERVAL;
144 ddr->sdram_data_init = CFG_DDR_DATA_INIT;
145 ddr->sdram_clk_cntl = CFG_DDR_CLK_CTRL;
146 ddr->sdram_ocd_cntl = CFG_DDR_OCD_CTRL;
147 ddr->sdram_ocd_status = CFG_DDR_OCD_STATUS;
149 #if defined (CONFIG_DDR_ECC)
150 ddr->err_disable = 0x0000008D;
151 ddr->err_sbe = 0x00ff0000;
157 #if defined (CONFIG_DDR_ECC)
158 /* Enable ECC checking */
159 ddr->sdram_cfg_1 = (CFG_DDR_CONTROL | 0x20000000);
161 ddr->sdram_cfg_1 = CFG_DDR_CONTROL;
162 ddr->sdram_cfg_2 = CFG_DDR_CONTROL2;
168 return CFG_SDRAM_SIZE * 1024 * 1024;
170 #endif /* !defined(CONFIG_SPD_EEPROM) */
173 #if defined(CONFIG_PCI)
175 * Initialize PCI Devices, report devices found.
178 #ifndef CONFIG_PCI_PNP
179 static struct pci_config_table pci_fsl86xxads_config_table[] = {
180 {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
181 PCI_IDSEL_NUMBER, PCI_ANY_ID,
182 pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
184 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER}},
190 static struct pci_controller pci1_hose = {
191 #ifndef CONFIG_PCI_PNP
192 config_table:pci_mpc86xxcts_config_table
195 #endif /* CONFIG_PCI */
198 static struct pci_controller pci2_hose;
199 #endif /* CONFIG_PCI2 */
201 int first_free_busno = 0;
204 void pci_init_board(void)
206 volatile immap_t *immap = (immap_t *) CFG_CCSRBAR;
207 volatile ccsr_gur_t *gur = &immap->im_gur;
208 uint devdisr = gur->devdisr;
209 uint io_sel = (gur->pordevsr & MPC8641_PORDEVSR_IO_SEL)
210 >> MPC8641_PORDEVSR_IO_SEL_SHIFT;
214 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR;
215 extern void fsl_pci_init(struct pci_controller *hose);
216 struct pci_controller *hose = &pci1_hose;
218 uint host1_agent = (gur->porbmsr & MPC8641_PORBMSR_HA)
219 >> MPC8641_PORBMSR_HA_SHIFT;
220 uint pex1_agent = (host1_agent == 0) || (host1_agent == 1);
222 if ((io_sel == 2 || io_sel == 3 || io_sel == 5
223 || io_sel == 6 || io_sel == 7 || io_sel == 0xF)
224 && !(devdisr & MPC86xx_DEVDISR_PCIEX1)) {
225 debug("PCI-EXPRESS 1: %s \n", pex1_agent ? "Agent" : "Host");
226 debug("0x%08x=0x%08x ", &pci->pme_msg_det, pci->pme_msg_det);
227 if (pci->pme_msg_det) {
228 pci->pme_msg_det = 0xffffffff;
229 debug(" with errors. Clearing. Now 0x%08x",
235 pci_set_region(hose->regions + 0,
239 PCI_REGION_MEM | PCI_REGION_MEMORY);
241 /* outbound memory */
242 pci_set_region(hose->regions + 1,
249 pci_set_region(hose->regions + 2,
255 hose->region_count = 3;
257 hose->first_busno=first_free_busno;
258 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
262 first_free_busno=hose->last_busno+1;
263 printf (" PCI-EXPRESS 1 on bus %02x - %02x\n",
264 hose->first_busno,hose->last_busno);
267 * Activate ULI1575 legacy chip by performing a fake
268 * memory access. Needed to make ULI RTC work.
270 in_be32((unsigned *) ((char *)(CFG_PCI1_MEM_BASE
271 + CFG_PCI1_MEM_SIZE - 0x1000000)));
274 puts("PCI-EXPRESS 1: Disabled\n");
278 puts("PCI-EXPRESS1: Disabled\n");
279 #endif /* CONFIG_PCI1 */
283 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI2_ADDR;
284 extern void fsl_pci_init(struct pci_controller *hose);
285 struct pci_controller *hose = &pci2_hose;
289 pci_set_region(hose->regions + 0,
293 PCI_REGION_MEM | PCI_REGION_MEMORY);
295 /* outbound memory */
296 pci_set_region(hose->regions + 1,
303 pci_set_region(hose->regions + 2,
309 hose->region_count = 3;
311 hose->first_busno=first_free_busno;
312 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
316 first_free_busno=hose->last_busno+1;
317 printf (" PCI-EXPRESS 2 on bus %02x - %02x\n",
318 hose->first_busno,hose->last_busno);
321 puts("PCI-EXPRESS 2: Disabled\n");
322 #endif /* CONFIG_PCI2 */
327 #if defined(CONFIG_OF_BOARD_SETUP)
330 ft_board_setup(void *blob, bd_t *bd)
335 ft_cpu_setup(blob, bd);
337 node = fdt_path_offset(blob, "/aliases");
341 path = fdt_getprop(blob, node, "pci0", NULL);
343 tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno;
344 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
348 path = fdt_getprop(blob, node, "pci1", NULL);
350 tmp[1] = pci2_hose.last_busno - pci2_hose.first_busno;
351 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
361 * Reads the FPGA on board for CONFIG_SYS_CLK_FREQ
365 get_board_sys_clk(ulong dummy)
367 u8 i, go_bit, rd_clks;
370 go_bit = in8(PIXIS_BASE + PIXIS_VCTL);
373 rd_clks = in8(PIXIS_BASE + PIXIS_VCFGEN0);
377 * Only if both go bit and the SCLK bit in VCFGEN0 are set
378 * should we be using the AUX register. Remember, we also set the
379 * GO bit to boot from the alternate bank on the on-board flash
384 i = in8(PIXIS_BASE + PIXIS_AUX);
386 i = in8(PIXIS_BASE + PIXIS_SPD);
388 i = in8(PIXIS_BASE + PIXIS_SPD);