2 * Copyright 2006, 2007, 2010 Freescale Semiconductor.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <asm/processor.h>
26 #include <asm/immap_86xx.h>
27 #include <asm/fsl_pci.h>
28 #include <asm/fsl_ddr_sdram.h>
31 #include <fdt_support.h>
34 phys_size_t fixed_sdram(void);
36 int board_early_init_f(void)
44 u8 *pixis_base = (u8 *)PIXIS_BASE;
46 printf ("Board: MPC8641HPCN, Sys ID: 0x%02x, "
47 "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
48 in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
49 in_8(pixis_base + PIXIS_PVER));
51 vboot = in_8(pixis_base + PIXIS_VBOOT);
52 if (vboot & PIXIS_VBOOT_FMAP)
53 printf ("vBank: %d\n", ((vboot & PIXIS_VBOOT_FBANK) >> 6));
57 #ifdef CONFIG_PHYS_64BIT
58 printf (" 36-bit physical address map\n");
64 initdram(int board_type)
66 phys_size_t dram_size = 0;
68 #if defined(CONFIG_SPD_EEPROM)
69 dram_size = fsl_ddr_sdram();
71 dram_size = fixed_sdram();
74 setup_ddr_bat(dram_size);
81 #if !defined(CONFIG_SPD_EEPROM)
83 * Fixed sdram init -- doesn't use serial presence detect.
88 #if !defined(CONFIG_SYS_RAMBOOT)
89 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
90 volatile ccsr_ddr_t *ddr = &immap->im_ddr1;
92 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
93 ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
94 ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
95 ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
96 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
97 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
98 ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
99 ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
100 ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
101 ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
102 ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
103 ddr->sdram_ocd_cntl = CONFIG_SYS_DDR_OCD_CTRL;
104 ddr->sdram_ocd_status = CONFIG_SYS_DDR_OCD_STATUS;
106 #if defined (CONFIG_DDR_ECC)
107 ddr->err_disable = 0x0000008D;
108 ddr->err_sbe = 0x00ff0000;
114 #if defined (CONFIG_DDR_ECC)
115 /* Enable ECC checking */
116 ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL | 0x20000000);
118 ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
119 ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;
125 return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
127 #endif /* !defined(CONFIG_SPD_EEPROM) */
130 #if defined(CONFIG_PCI)
131 static struct pci_controller pcie1_hose;
132 #endif /* CONFIG_PCI */
135 static struct pci_controller pcie2_hose;
136 #endif /* CONFIG_PCIE2 */
138 int first_free_busno = 0;
140 void pci_init_board(void)
142 struct fsl_pci_info pci_info[2];
147 volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR;
148 volatile ccsr_gur_t *gur = &immap->im_gur;
149 uint devdisr = in_be32(&gur->devdisr);
150 uint io_sel = (gur->pordevsr & MPC8641_PORDEVSR_IO_SEL)
151 >> MPC8641_PORDEVSR_IO_SEL_SHIFT;
152 int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
154 if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIEX1)) {
155 SET_STD_PCIE_INFO(pci_info[num], 1);
156 pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
157 printf("PCIE1: connected to ULI as %s (base addr %lx)\n",
158 pcie_ep ? "Endpoint" : "Root Complex",
160 first_free_busno = fsl_pci_init_port(&pci_info[num++],
161 &pcie1_hose, first_free_busno);
164 * Activate ULI1575 legacy chip by performing a fake
165 * memory access. Needed to make ULI RTC work.
167 in_be32((unsigned *) ((char *)(CONFIG_SYS_PCIE1_MEM_VIRT
168 + CONFIG_SYS_PCIE1_MEM_SIZE - 0x1000000)));
171 puts("PCIE1: disabled\n");
174 puts("PCIE1: disabled\n");
175 #endif /* CONFIG_PCIE1 */
178 SET_STD_PCIE_INFO(pci_info[num], 2);
179 pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
180 printf("PCIE2: connected as %s (base addr %lx)\n",
181 pcie_ep ? "Endpoint" : "Root Complex",
183 first_free_busno = fsl_pci_init_port(&pci_info[num++],
184 &pcie2_hose, first_free_busno);
186 puts("PCIE2: disabled\n");
187 #endif /* CONFIG_PCIE2 */
192 #if defined(CONFIG_OF_BOARD_SETUP)
194 ft_board_setup(void *blob, bd_t *bd)
200 ft_cpu_setup(blob, bd);
205 * Warn if it looks like the device tree doesn't match u-boot.
206 * This is just an estimation, based on the location of CCSR,
207 * which is defined by the "reg" property in the soc node.
209 off = fdt_path_offset(blob, "/soc8641");
210 addrcells = (u32 *)fdt_getprop(blob, 0, "#address-cells", NULL);
211 tmp = (u64 *)fdt_getprop(blob, off, "reg", NULL);
215 if (addrcells && (*addrcells == 1))
220 if (addr != CONFIG_SYS_CCSRBAR_PHYS)
221 printf("WARNING: The CCSRBAR address in your .dts "
222 "does not match the address of the CCSR "
223 "in u-boot. This means your .dts might "
232 * Reads the FPGA on board for CONFIG_SYS_CLK_FREQ
236 get_board_sys_clk(ulong dummy)
238 u8 i, go_bit, rd_clks;
240 u8 *pixis_base = (u8 *)PIXIS_BASE;
242 go_bit = in_8(pixis_base + PIXIS_VCTL);
245 rd_clks = in_8(pixis_base + PIXIS_VCFGEN0);
249 * Only if both go bit and the SCLK bit in VCFGEN0 are set
250 * should we be using the AUX register. Remember, we also set the
251 * GO bit to boot from the alternate bank on the on-board flash
256 i = in_8(pixis_base + PIXIS_AUX);
258 i = in_8(pixis_base + PIXIS_SPD);
260 i = in_8(pixis_base + PIXIS_SPD);
295 int board_eth_init(bd_t *bis)
297 /* Initialize TSECs */
299 return pci_eth_init(bis);
302 void board_reset(void)
304 u8 *pixis_base = (u8 *)PIXIS_BASE;
306 out_8(pixis_base + PIXIS_RST, 0);
313 extern void cpu_mp_lmb_reserve(struct lmb *lmb);
315 void board_lmb_reserve(struct lmb *lmb)
317 cpu_mp_lmb_reserve(lmb);