git.sur5r.net Git - u-boot/blob - board/freescale/mx31pdk/lowlevel_init.S

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * (C) Copyright 2009 Magnus Lilja <lilja.magnus@gmail.com>
   4  */
   5
   6 #include <config.h>
   7 #include <asm/arch/imx-regs.h>
   8 #include <asm/macro.h>
   9
  10 .globl lowlevel_init
  11 lowlevel_init:
  12         /* Also setup the Peripheral Port Remap register inside the core */
  13         ldr     r0, =ARM_PPMRR      /* start from AIPS 2GB region */
  14         mcr     p15, 0, r0, c15, c2, 4
  15
  16         write32 IPU_CONF, IPU_CONF_DI_EN
  17         write32 CCM_CCMR, CCM_CCMR_SETUP
  18
  19         wait_timer      0x40000
  20
  21         write32 CCM_CCMR, CCM_CCMR_SETUP | CCMR_MPE
  22         write32 CCM_CCMR, (CCM_CCMR_SETUP | CCMR_MPE) & ~CCMR_MDS
  23
  24         /* Set up clock to 532MHz */
  25         write32 CCM_PDR0, CCM_PDR0_SETUP_532MHZ
  26         write32 CCM_MPCTL, CCM_MPCTL_SETUP_532MHZ
  27
  28         write32 CCM_SPCTL, PLL_PD(1) | PLL_MFD(4) | PLL_MFI(12) | PLL_MFN(1)
  29
  30         /* Set up MX31 DDR pins */
  31         write32 IOMUXC_SW_PAD_CTL_SDCKE1_SDCLK_SDCLK_B, 0
  32         write32 IOMUXC_SW_PAD_CTL_CAS_SDWE_SDCKE0, 0
  33         write32 IOMUXC_SW_PAD_CTL_BCLK_RW_RAS, 0
  34         write32 IOMUXC_SW_PAD_CTL_CS2_CS3_CS4, 0x1000
  35         write32 IOMUXC_SW_PAD_CTL_DQM3_EB0_EB1, 0
  36         write32 IOMUXC_SW_PAD_CTL_DQM0_DQM1_DQM2, 0
  37         write32 IOMUXC_SW_PAD_CTL_SD29_SD30_SD31, 0
  38         write32 IOMUXC_SW_PAD_CTL_SD26_SD27_SD28, 0
  39         write32 IOMUXC_SW_PAD_CTL_SD23_SD24_SD25, 0
  40         write32 IOMUXC_SW_PAD_CTL_SD20_SD21_SD22, 0
  41         write32 IOMUXC_SW_PAD_CTL_SD17_SD18_SD19, 0
  42         write32 IOMUXC_SW_PAD_CTL_SD14_SD15_SD16, 0
  43         write32 IOMUXC_SW_PAD_CTL_SD11_SD12_SD13, 0
  44         write32 IOMUXC_SW_PAD_CTL_SD8_SD9_SD10, 0
  45         write32 IOMUXC_SW_PAD_CTL_SD5_SD6_SD7, 0
  46         write32 IOMUXC_SW_PAD_CTL_SD2_SD3_SD4, 0
  47         write32 IOMUXC_SW_PAD_CTL_SDBA0_SD0_SD1, 0
  48         write32 IOMUXC_SW_PAD_CTL_A24_A25_SDBA1, 0
  49         write32 IOMUXC_SW_PAD_CTL_A21_A22_A23, 0
  50         write32 IOMUXC_SW_PAD_CTL_A18_A19_A20, 0
  51         write32 IOMUXC_SW_PAD_CTL_A15_A16_A17, 0
  52         write32 IOMUXC_SW_PAD_CTL_A12_A13_A14, 0
  53         write32 IOMUXC_SW_PAD_CTL_A10_MA10_A11, 0
  54         write32 IOMUXC_SW_PAD_CTL_A7_A8_A9, 0
  55         write32 IOMUXC_SW_PAD_CTL_A4_A5_A6, 0
  56         write32 IOMUXC_SW_PAD_CTL_A1_A2_A3, 0
  57         write32 IOMUXC_SW_PAD_CTL_VPG0_VPG1_A0, 0
  58
  59         /* Set up MX31 DDR Memory Controller */
  60         write32 WEIM_ESDMISC, ESDMISC_MDDR_SETUP
  61         write32 WEIM_ESDCFG0, ESDCFG0_MDDR_SETUP
  62
  63         /* Perform DDR init sequence */
  64         write32 WEIM_ESDCTL0, ESDCTL_PRECHARGE
  65         write32 CSD0_BASE | 0x0f00, 0x12344321
  66         write32 WEIM_ESDCTL0, ESDCTL_AUTOREFRESH
  67         write32 CSD0_BASE, 0x12344321
  68         write32 CSD0_BASE, 0x12344321
  69         write32 WEIM_ESDCTL0, ESDCTL_LOADMODEREG
  70         write8  CSD0_BASE | 0x00000033, 0xda
  71         write8  CSD0_BASE | 0x01000000, 0xff
  72         write32 WEIM_ESDCTL0, ESDCTL_RW
  73         write32 CSD0_BASE, 0xDEADBEEF
  74         write32 WEIM_ESDMISC, ESDMISC_MDDR_RESET_DL
  75
  76         mov     pc, lr