2 * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
4 * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 #include <asm/arch/imx-regs.h>
24 #include <generated/asm-offsets.h>
26 #include <asm/arch/lowlevel_macro.S>
34 .macro check_soc_version ret, tmp
35 ldr \tmp, =IIM_BASE_ADDR
36 ldr \ret, [\tmp, #IIM_SREV]
38 moveq \tmp, #ROMPATCH_REV
40 moveq \ret, \ret, lsl #4
41 addne \ret, \ret, #0x10
44 /* CPLD on CS5 setup */
45 .macro init_debug_board
46 ldr r0, =DBG_BASE_ADDR
47 ldr r1, =DBG_CSCR_U_CONFIG
49 ldr r1, =DBG_CSCR_L_CONFIG
51 ldr r1, =DBG_CSCR_A_CONFIG
57 ldr r0, =CCM_BASE_ADDR
59 /* default CLKO to 1/32 of the ARM core*/
60 ldr r1, [r0, #CLKCTL_COSR]
61 bic r1, r1, #0x00000FF00
62 bic r1, r1, #0x0000000FF
66 str r1, [r0, #CLKCTL_COSR]
68 ldr r2, =CCM_CCMR_CONFIG
69 str r2, [r0, #CLKCTL_CCMR]
71 check_soc_version r1, r2
73 ldrhs r3, =CCM_MPLL_532_HZ
75 ldr r2, [r0, #CLKCTL_PDR0]
76 tst r2, #CLKMODE_CONSUMER
77 ldrne r3, =CCM_MPLL_532_HZ /* consumer path*/
78 ldreq r3, =CCM_MPLL_399_HZ /* auto path*/
80 str r3, [r0, #CLKCTL_MPCTL]
82 ldr r1, =CCM_PPLL_300_HZ
83 str r1, [r0, #CLKCTL_PPCTL]
85 ldr r1, =CCM_PDR0_CONFIG
87 str r1, [r0, #CLKCTL_PDR0]
89 ldr r1, [r0, #CLKCTL_CGR0]
90 orr r1, r1, #0x0C300000
91 str r1, [r0, #CLKCTL_CGR0]
93 ldr r1, [r0, #CLKCTL_CGR1]
94 orr r1, r1, #0x00000C00
95 orr r1, r1, #0x00000003
96 str r1, [r0, #CLKCTL_CGR1]
98 ldr r1, [r0, #CLKCTL_CGR2]
99 orr r1, r1, #0x00C00000
100 str r1, [r0, #CLKCTL_CGR2]
104 ldr r0, =ESDCTL_BASE_ADDR
109 /*ip(r12) has used to save lr register in upper calling*/
114 mov r1, #CSD0_BASE_ADDR
119 mov r1, #CSD1_BASE_ADDR
125 ldr r3, =ESDCTL_DELAY_LINE5
144 cmp pc, #PHYS_SDRAM_1
146 cmp pc, #(PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)
159 * r0: ESDCTL control base, r1: sdram slot base
160 * r2: DDR type(0:DDR2, 1:MDDR) r3, r4:working base
165 orreq r3, r3, #0x300 /*DDR2*/
176 ldreq r3, =ESDCTL_DDR2_CONFIG
177 ldrne r3, =ESDCTL_MDDR_CONFIG
178 cmp r1, #CSD1_BASE_ADDR
182 ldr r3, =ESDCTL_0x92220000
186 ldr r4, =ESDCTL_PRECHARGE
192 cmp r1, #CSD1_BASE_ADDR
193 ldr r3, =ESDCTL_0xB2220000
197 ldr r4, =ESDCTL_DDR2_EMR2
199 ldr r4, =ESDCTL_DDR2_EMR3
201 ldr r4, =ESDCTL_DDR2_EN_DLL
203 ldr r4, =ESDCTL_DDR2_RESET_DLL
206 ldr r3, =ESDCTL_0x92220000
210 ldr r4, =ESDCTL_PRECHARGE
214 cmp r1, #CSD1_BASE_ADDR
215 ldr r3, =ESDCTL_0xA2220000
222 ldr r3, =ESDCTL_0xB2220000
226 ldreq r4, =ESDCTL_DDR2_MR
227 ldrne r4, =ESDCTL_MDDR_MR
230 ldreq r4, =ESDCTL_DDR2_OCD_DEFAULT
232 ldreq r4, =ESDCTL_DDR2_EN_DLL
233 ldrne r4, =ESDCTL_MDDR_EMR
236 cmp r1, #CSD1_BASE_ADDR
237 ldr r3, =ESDCTL_0x82228080