2 * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
4 * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 #include <asm/arch/imx-regs.h>
24 #include <asm/arch/asm-offsets.h>
33 .macro check_soc_version ret, tmp
34 ldr \tmp, =IIM_BASE_ADDR
35 ldr \ret, [\tmp, #IIM_SREV]
37 moveq \tmp, #ROMPATCH_REV
39 moveq \ret, \ret, lsl #4
40 addne \ret, \ret, #0x10
44 * AIPS setup - Only setup MPROTx registers.
45 * The PACR default values are good.
49 * Set all MPROTx to be non-bufferable, trusted for R/W,
50 * not forced to user-mode.
52 ldr r0, =AIPS1_BASE_ADDR
53 ldr r1, =AIPS_MPR_CONFIG
56 ldr r0, =AIPS2_BASE_ADDR
61 * Clear the on and off peripheral modules Supervisor Protect bit
62 * for SDMA to access them. Did not change the AIPS control registers
63 * (offset 0x20) access type
65 ldr r0, =AIPS1_BASE_ADDR
66 ldr r1, =AIPS_OPACR_CONFIG
72 ldr r0, =AIPS2_BASE_ADDR
80 /* MAX (Multi-Layer AHB Crossbar Switch) setup */
82 ldr r0, =MAX_BASE_ADDR
83 /* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */
84 ldr r1, =MAX_MPR_CONFIG
85 str r1, [r0, #0x000] /* for S0 */
86 str r1, [r0, #0x100] /* for S1 */
87 str r1, [r0, #0x200] /* for S2 */
88 str r1, [r0, #0x300] /* for S3 */
89 str r1, [r0, #0x400] /* for S4 */
90 /* SGPCR - always park on last master */
91 ldr r1, =MAX_SGPCR_CONFIG
92 str r1, [r0, #0x010] /* for S0 */
93 str r1, [r0, #0x110] /* for S1 */
94 str r1, [r0, #0x210] /* for S2 */
95 str r1, [r0, #0x310] /* for S3 */
96 str r1, [r0, #0x410] /* for S4 */
97 /* MGPCR - restore default values */
98 ldr r1, =MAX_MGPCR_CONFIG
99 str r1, [r0, #0x800] /* for M0 */
100 str r1, [r0, #0x900] /* for M1 */
101 str r1, [r0, #0xA00] /* for M2 */
102 str r1, [r0, #0xB00] /* for M3 */
103 str r1, [r0, #0xC00] /* for M4 */
104 str r1, [r0, #0xD00] /* for M5 */
109 /* Configure M3IF registers */
110 ldr r1, =M3IF_BASE_ADDR
112 * M3IF Control Register (M3IFCTL)
113 * MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000
114 * MRRP[1] = L2CC1 not on priority list (0 << 0) = 0x00000000
115 * MRRP[2] = MBX not on priority list (0 << 0) = 0x00000000
116 * MRRP[3] = MAX1 not on priority list (0 << 0) = 0x00000000
117 * MRRP[4] = SDMA not on priority list (0 << 0) = 0x00000000
118 * MRRP[5] = MPEG4 not on priority list (0 << 0) = 0x00000000
119 * MRRP[6] = IPU1 on priority list (1 << 6) = 0x00000040
120 * MRRP[7] = IPU2 not on priority list (0 << 0) = 0x00000000
125 str r0, [r1] /* M3IF control reg */
128 /* CPLD on CS5 setup */
129 .macro init_debug_board
130 ldr r0, =DBG_BASE_ADDR
131 ldr r1, =DBG_CSCR_U_CONFIG
133 ldr r1, =DBG_CSCR_L_CONFIG
135 ldr r1, =DBG_CSCR_A_CONFIG
141 ldr r0, =CCM_BASE_ADDR
143 /* default CLKO to 1/32 of the ARM core*/
144 ldr r1, [r0, #CLKCTL_COSR]
145 bic r1, r1, #0x00000FF00
146 bic r1, r1, #0x0000000FF
150 str r1, [r0, #CLKCTL_COSR]
152 ldr r2, =CCM_CCMR_CONFIG
153 str r2, [r0, #CLKCTL_CCMR]
155 check_soc_version r1, r2
156 cmp r1, #CHIP_REV_2_0
157 ldrhs r3, =CCM_MPLL_532_HZ
159 ldr r2, [r0, #CLKCTL_PDR0]
160 tst r2, #CLKMODE_CONSUMER
161 ldrne r3, =CCM_MPLL_532_HZ /* consumer path*/
162 ldreq r3, =CCM_MPLL_399_HZ /* auto path*/
164 str r3, [r0, #CLKCTL_MPCTL]
166 ldr r1, =CCM_PPLL_300_HZ
167 str r1, [r0, #CLKCTL_PPCTL]
169 ldr r1, =CCM_PDR0_CONFIG
170 bic r1, r1, #0x800000
171 str r1, [r0, #CLKCTL_PDR0]
173 ldr r1, [r0, #CLKCTL_CGR0]
174 orr r1, r1, #0x0C300000
175 str r1, [r0, #CLKCTL_CGR0]
177 ldr r1, [r0, #CLKCTL_CGR1]
178 orr r1, r1, #0x00000C00
179 orr r1, r1, #0x00000003
180 str r1, [r0, #CLKCTL_CGR1]
184 ldr r0, =ESDCTL_BASE_ADDR
189 /*ip(r12) has used to save lr register in upper calling*/
194 mov r1, #CSD0_BASE_ADDR
199 blne setup_sdram_bank
204 ldr r3, =ESDCTL_DELAY_LINE5
212 mrc 15, 0, r1, c1, c0, 0
214 mrc 15, 0, r0, c1, c0, 1
216 mcr 15, 0, r0, c1, c0, 1
219 /* Set unaligned access enable */
222 /* Set low int latency enable */
225 mcr 15, 0, r1, c1, c0, 0
229 /* Set branch prediction enable */
230 mcr 15, 0, r0, c15, c2, 4
232 mcr 15, 0, r0, c7, c7, 0 /* invalidate I cache and D cache */
233 mcr 15, 0, r0, c8, c7, 0 /* invalidate TLBs */
234 mcr 15, 0, r0, c7, c10, 4 /* Drain the write buffer */
237 * initializes very early AIPS
238 * Then it also initializes Multi-Layer AHB Crossbar Switch,
240 * Also setup the Peripheral Port Remap register inside the core
242 ldr r0, =0x40000015 /* start from AIPS 2GB region */
243 mcr p15, 0, r0, c15, c2, 4
254 cmp pc, #PHYS_SDRAM_1
256 cmp pc, #(PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)
269 * r0: ESDCTL control base, r1: sdram slot base
270 * r2: DDR type(0:DDR2, 1:MDDR) r3, r4:working base
275 orreq r3, r3, #0x300 /*DDR2*/
286 ldreq r3, =ESDCTL_DDR2_CONFIG
287 ldrne r3, =ESDCTL_MDDR_CONFIG
288 cmp r1, #CSD1_BASE_ADDR
292 ldr r3, =ESDCTL_0x92220000
296 ldr r4, =ESDCTL_PRECHARGE
302 cmp r1, #CSD1_BASE_ADDR
303 ldr r3, =ESDCTL_0xB2220000
307 ldr r4, =ESDCTL_DDR2_EMR2
309 ldr r4, =ESDCTL_DDR2_EMR3
311 ldr r4, =ESDCTL_DDR2_EN_DLL
313 ldr r4, =ESDCTL_DDR2_RESET_DLL
316 ldr r3, =ESDCTL_0x92220000
320 ldr r4, =ESDCTL_PRECHARGE
324 cmp r1, #CSD1_BASE_ADDR
325 ldr r3, =ESDCTL_0xA2220000
332 ldr r3, =ESDCTL_0xB2220000
336 ldreq r4, =ESDCTL_DDR2_MR
337 ldrne r4, =ESDCTL_MDDR_MR
340 ldreq r4, =ESDCTL_DDR2_OCD_DEFAULT
342 ldreq r4, =ESDCTL_DDR2_EN_DLL
343 ldrne r4, =ESDCTL_MDDR_EMR
346 cmp r1, #CSD1_BASE_ADDR
347 ldr r3, =ESDCTL_0x82228080