2 * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
4 * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
6 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/imx-regs.h>
11 #include <generated/asm-offsets.h>
13 #include <asm/arch/lowlevel_macro.S>
21 .macro check_soc_version ret, tmp
22 ldr \tmp, =IIM_BASE_ADDR
23 ldr \ret, [\tmp, #IIM_SREV]
25 moveq \tmp, #ROMPATCH_REV
27 moveq \ret, \ret, lsl #4
28 addne \ret, \ret, #0x10
31 /* CPLD on CS5 setup */
32 .macro init_debug_board
33 ldr r0, =DBG_BASE_ADDR
34 ldr r1, =DBG_CSCR_U_CONFIG
36 ldr r1, =DBG_CSCR_L_CONFIG
38 ldr r1, =DBG_CSCR_A_CONFIG
44 ldr r0, =CCM_BASE_ADDR
46 /* default CLKO to 1/32 of the ARM core*/
47 ldr r1, [r0, #CLKCTL_COSR]
48 bic r1, r1, #0x00000FF00
49 bic r1, r1, #0x0000000FF
53 str r1, [r0, #CLKCTL_COSR]
55 ldr r2, =CCM_CCMR_CONFIG
56 str r2, [r0, #CLKCTL_CCMR]
58 check_soc_version r1, r2
60 ldrhs r3, =CCM_MPLL_532_HZ
62 ldr r2, [r0, #CLKCTL_PDR0]
63 tst r2, #CLKMODE_CONSUMER
64 ldrne r3, =CCM_MPLL_532_HZ /* consumer path*/
65 ldreq r3, =CCM_MPLL_399_HZ /* auto path*/
67 str r3, [r0, #CLKCTL_MPCTL]
69 ldr r1, =CCM_PPLL_300_HZ
70 str r1, [r0, #CLKCTL_PPCTL]
72 ldr r1, =CCM_PDR0_CONFIG
74 str r1, [r0, #CLKCTL_PDR0]
76 ldr r1, [r0, #CLKCTL_CGR0]
77 orr r1, r1, #0x0C300000
78 str r1, [r0, #CLKCTL_CGR0]
80 ldr r1, [r0, #CLKCTL_CGR1]
81 orr r1, r1, #0x00000C00
82 orr r1, r1, #0x00000003
83 str r1, [r0, #CLKCTL_CGR1]
85 ldr r1, [r0, #CLKCTL_CGR2]
86 orr r1, r1, #0x00C00000
87 str r1, [r0, #CLKCTL_CGR2]
91 ldr r0, =ESDCTL_BASE_ADDR
96 /*ip(r12) has used to save lr register in upper calling*/
101 mov r1, #CSD0_BASE_ADDR
106 mov r1, #CSD1_BASE_ADDR
112 ldr r3, =ESDCTL_DELAY_LINE5
131 cmp pc, #PHYS_SDRAM_1
133 cmp pc, #(PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)
146 * r0: ESDCTL control base, r1: sdram slot base
147 * r2: DDR type(0:DDR2, 1:MDDR) r3, r4:working base
152 orreq r3, r3, #0x300 /*DDR2*/
163 ldreq r3, =ESDCTL_DDR2_CONFIG
164 ldrne r3, =ESDCTL_MDDR_CONFIG
165 cmp r1, #CSD1_BASE_ADDR
169 ldr r3, =ESDCTL_0x92220000
173 ldr r4, =ESDCTL_PRECHARGE
179 cmp r1, #CSD1_BASE_ADDR
180 ldr r3, =ESDCTL_0xB2220000
184 ldr r4, =ESDCTL_DDR2_EMR2
186 ldr r4, =ESDCTL_DDR2_EMR3
188 ldr r4, =ESDCTL_DDR2_EN_DLL
190 ldr r4, =ESDCTL_DDR2_RESET_DLL
193 ldr r3, =ESDCTL_0x92220000
197 ldr r4, =ESDCTL_PRECHARGE
201 cmp r1, #CSD1_BASE_ADDR
202 ldr r3, =ESDCTL_0xA2220000
209 ldr r3, =ESDCTL_0xB2220000
213 ldreq r4, =ESDCTL_DDR2_MR
214 ldrne r4, =ESDCTL_MDDR_MR
217 ldreq r4, =ESDCTL_DDR2_OCD_DEFAULT
219 ldreq r4, =ESDCTL_DDR2_EN_DLL
220 ldrne r4, =ESDCTL_MDDR_EMR
223 cmp r1, #CSD1_BASE_ADDR
224 ldr r3, =ESDCTL_0x82228080