3 * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
5 * (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #ifndef __BOARD_MX35_3STACK_H
27 #define __BOARD_MX35_3STACK_H
29 #define AIPS_MPR_CONFIG 0x77777777
30 #define AIPS_OPACR_CONFIG 0x00000000
32 /* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */
33 #define MAX_MPR_CONFIG 0x00302154
34 /* SGPCR - always park on last master */
35 #define MAX_SGPCR_CONFIG 0x00000010
36 /* MGPCR - restore default values */
37 #define MAX_MGPCR_CONFIG 0x00000000
40 * M3IF Control Register (M3IFCTL)
41 * MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000
42 * MRRP[1] = L2CC1 not on priority list (0 << 0) = 0x00000000
43 * MRRP[2] = MBX not on priority list (0 << 0) = 0x00000000
44 * MRRP[3] = MAX1 not on priority list (0 << 0) = 0x00000000
45 * MRRP[4] = SDMA not on priority list (0 << 0) = 0x00000000
46 * MRRP[5] = MPEG4 not on priority list (0 << 0) = 0x00000000
47 * MRRP[6] = IPU1 on priority list (1 << 6) = 0x00000040
48 * MRRP[7] = IPU2 not on priority list (0 << 0) = 0x00000000
52 #define M3IF_CONFIG 0x00000040
54 #define DBG_BASE_ADDR WEIM_CTRL_CS5
55 #define DBG_CSCR_U_CONFIG 0x0000D843
56 #define DBG_CSCR_L_CONFIG 0x22252521
57 #define DBG_CSCR_A_CONFIG 0x22220A00
59 #define CCM_CCMR_CONFIG 0x003F4208
60 #define CCM_PDR0_CONFIG 0x00801000
63 #define ESDCTL_0x92220000 0x92220000
64 #define ESDCTL_0xA2220000 0xA2220000
65 #define ESDCTL_0xB2220000 0xB2220000
66 #define ESDCTL_0x82228080 0x82228080
68 #define ESDCTL_PRECHARGE 0x00000400
70 #define ESDCTL_MDDR_CONFIG 0x007FFC3F
71 #define ESDCTL_MDDR_MR 0x00000033
72 #define ESDCTL_MDDR_EMR 0x02000000
74 #define ESDCTL_DDR2_CONFIG 0x007FFC3F
75 #define ESDCTL_DDR2_EMR2 0x04000000
76 #define ESDCTL_DDR2_EMR3 0x06000000
77 #define ESDCTL_DDR2_EN_DLL 0x02000400
78 #define ESDCTL_DDR2_RESET_DLL 0x00000333
79 #define ESDCTL_DDR2_MR 0x00000233
80 #define ESDCTL_DDR2_OCD_DEFAULT 0x02000780
82 #define ESDCTL_DELAY_LINE5 0x00F49F00
83 #endif /* __BOARD_MX35_3STACK_H */